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The Role of the Gate Resistance and Device Variability on the Dynamic Performance of Parallel SiC Power MOSFETs | IEEE Conference Publication | IEEE Xplore

The Role of the Gate Resistance and Device Variability on the Dynamic Performance of Parallel SiC Power MOSFETs


Abstract:

This paper presents an analysis of the fast switching transients with parallel SiC power MOSFETs. It is observed that two SiC power MOSFETs in parallel fail during the do...Show More

Abstract:

This paper presents an analysis of the fast switching transients with parallel SiC power MOSFETs. It is observed that two SiC power MOSFETs in parallel fail during the double-pulse-test measurements at turn-off events for high load currents. The failure originates from the internal oscillations caused by the circuit layout, package parasitics, and device variability. An advanced modeling procedure taking into account the de-vice process variations, the internal distributed gate resistance, and the broadband electromagnetic parasitic behavior of the switching circuit and package was used to analyze the internal oscillations, which could not be probed by any measurements. It is shown that the channel doping variation, causing threshold voltage V_{\text{th}} mismatch, can lead to a high gate stress during turn-off. An integrated lumped internal gate resistance R_{\text{g,int,L}} is demonstrated to be beneficial for the safe switching operation more than the intrinsic gate distributed resistance R_{\text{g,int,D}}.
Date of Conference: 02-06 June 2024
Date Added to IEEE Xplore: 09 July 2024
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Conference Location: Bremen, Germany
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I. Introduction

Silicon carbide (SiC) power MOSFETs are connected in parallel within multi-chip power modules to increase current capability for high power applications. The mismatch of the circuit and package parasitics, as well as the process related device variability [1], [2], can lead to uneven conditions during both conduction [3] and fast switching [4]. This non-uniformity has negative impact on long-term reliability and on gate voltage over/under-shoots potentially leading to failure during a single switching event. A higher gate resistance, both internal and external, is often used to reduce the switching speed and obtain reliable switching transients [5]. However, slow switching compromises the overall system efficiency due to higher switching losses. With smaller active area, SiC power MOSFETs feature also a higher internal gate resistance defined by the gate network consisting of aluminum metal runners and highly N-doped polysilicon [6]. Furthermore, is frequency (f-) dependent and determines the propagation of the gate signal across the die.

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