Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique

The node upset may occur in the memory cell if the charged particle from cosmos rays or packaging materials strikes the integrated circuit. Radiation-hardened-by-design (RHBD) techniques introduce redundant transistors in the SRAM cell to improve its ability of recovering from the undesired node upset. However, the extra redundant transistors may increase the number of sensitive nodes in the SRAM cell, which decreases its capability of node-upset tolerance in turn. This work proposes an RHBD 14T SRAM cell and an RHBD 16T SRAM cell. Both the proposed SRAM cells only have two sensitive nodes. The proposed SRAM cells are able to recover from all the SNU cases. The layout harden technique is used to protect the proposed cells from SEMNU, and the blank of the hardened layout is reused so the proposed 14T and 16T SRAM cells consume the same area. Although the proposed cells have more transistors, the hardened layout areas of NS-10T/ PS-10T/ RHD-12T/ RHBD-10T/ RHBD-10T[VLSI]/ QUCCE-12T are respectively $1.78\times $ / $1.78\times $ / $1.83\times $ / $1.78\times $ / $1.78\times $ / $1.99\times $ larger than that of the proposed cells. The reason is that the layout harden technique is easier to be applied to the proposed cells because they only have two sensitive nodes.

I. Introduction

The static random access memory (SRAM), which is widely used as cache in microprocessor or system-on-chip (SoC), plays a key role in optimizing the performance and reliability of computer systems [1], [2], [3]. In the radiation environment, charged particle from the cosmos rays or packaging materials severely impacts the reliability of an SRAM cell [4], [5]. The single event transient (SET) is the undesired pulse generated in the circuit node, if the radiation particle strikes the victim SRAM cell. It may flip the logic state of the struck node if the energy of the transient pulse is strong enough. The single event upset (SEU) may occur, if the effect of the transient pulse propagates to a storage node or the radiation particle strikes the storage node directly. The single node upset (SNU) occurs if the SEU upsets only one storage node, which is named as the single-event single-node upset (SESNU). The multiple node upset (MNU) occurs if the SEU upsets multiple storage nodes through the charge sharing effect, which is named as the single-event multi-node upset (SEMNU) [6], [7], [8]. It is predicted that the SRAM-based cache may even occupy 90% of the area of some SOCs [9], [10]. Therefore, the reliability of SRAM cell in the radiation environment is of great concern in the SOC design for the radiation environment applications.