A surface-mount photonic package with a photonic-wire-bonded glass interposer as a hybrid integration platform for co-packaged optics

Compound semiconductor optical devices have superior performance compared to Si Photonics (SiPh) devices. However, due to the requirement for a hermetic temperature-controlled package, integration with an Application Specific IC (ASIC) has been challenging. Therefore, we propose a novel surface-mount photonic package with a photonic-wire-bonded Glass Interposer (GIP) compatible to hermetic sealing and temperature controlling. The package enables the integration of an Optical Sub-Assembly (OSA) with the ASIC, allowing for reduced power consumption and improved high-frequency performance. In this package, both a Photonic IC (PIC) and an Electrical IC (EIC) driving the PIC are hermetically sealed between the GIP and a glass lid. A hermetic glass waveguide is used to extract the optical signal from the PIC, and the PIC is connected to the glass waveguide via photonic wires, realizing ultracompact high-density optical coupling. The photonic wire bonding between a SiPh-PIC and a glass waveguide substrate is demonstrated in this study, showing a coupling efficiency as small as -1.9 dB in the C-band. A hermetic Through Glass Via (TGV) is used to extract high-speed electrical signal from the EIC. Electromagnetic field analysis shows that resonance-free and low-loss high-frequency transmission characteristics over 120 GHz are available. The temperature control of the PIC is achieved by a Thermoelectric Cooler (TEC) through a thermally conductive hermetic medium such as TGVs and Si. Thermal analysis demonstrates the inhibition of thermal crosstalk from the EIC and the ability to achieve stable temperature control of the PIC. Based on these results, it is concluded that this package can serve as a hybrid integration platform for co-packaging the compound semiconductor OSA with the ASIC.

I. Introduction

Driven by the evolution of Artificial Intelligence (AI) and Machine Learning (ML) technology, the amount of data communication in a Data Center (DC) and High Performance Computing (HPC) is growing more than ever. As a signaling rate increases, high-frequency loss between an ASIC and an OSA becomes larger. It leads to severe power consumption of a compensation circuit such as an equalizer or a retimer, and there are high expectations on Co-Packaged Optics (CPO) that integrates the OSA and the ASIC closely [1]-[2]. SiPh in which optical modulators or photodiodes are integrated on a Si chip is becoming a standard platform for the CPO because it is highly compatible to advanced semiconductor packaging technology [3]-[5].