I. Introduction
Hardware implementations of cryptographic engines are susceptible to Power Side Channel Attacks (PSCA). The common practice of performing PSCA is to place an on-board series attack resistance (Rx), of 1Ω or larger, on the power-line (Vtarget) of the crypto-engine, to acquire voltage (or current) signatures. These signatures are then used to perform statistical analysis, such as Correlation Power Analysis (CPA) [1], to reveal the secret key of a cipher (Fig. 1). Several on-chip PSCA countermeasures have been proposed [2]–[6] to make it difficult to correlate power models in CPA and increase the Minimum Traces to Disclosure (MTD) of the secret key. While these measures make it harder to extract the key, they do not completely prevent PSCA. Hence, on-chip circuits to detect and prevent on-going PSCA are required.