Capacitance Modeling With Charge Partitions Covering Full-Region Operations of TFETs

An accurate physics-based capacitance model is developed covering full-region operations of silicon TFET (Si-TFET) with all biasing conditions. The intrinsic and parasitic capacitances are modeled by the surface-potential-based method and justified by calibrated TCAD simulations. To address the challenges of a classical physics-based model in calculating the charge partitions, an artificial neural network (ANN)-enhanced method is proposed to capture the terminal partition strategy, which features good smoothness and high accuracy. The results show a source terminal partition of the ambipolar region in the range of 90%–100%, and the drain partition of the normal region is in the range of 85%–100%, with in-between partitions of the transition regions. This ANN-enhanced physics-based model addresses the requirements of a TFET channel charge partition strategy and has been verified in circuit simulations with improved accuracy.

I. Introduction

TFETs are recognized as a type of promising steep-slope device with advantages, including sub-60-mV/dec subthreshold swing at room temperature [1], [2], lower leakage current compared with traditional CMOS devices [3], and compatibility with the CMOS fabrication process [4], [5]. Recently, TFET-based low-power consumption circuits have been proposed, such as TFET standard logic cells [6], [7], polymorphic gate logic circuits [8], SRAMs [9], [10], and NDR-skewed sense amplifiers [11]. TFET devices operate in the normal band-to-band tunneling (BTBT) region, ambipolar region, and forward p-i-n region in the above emerging circuits [6], [7], [8], [9], [10], [11]. Silicon TFET (Si-TFET) with low leakage circuit has been properly employed in the ultralow-power Internet of Things (IoT) chips, such as TFET-CMOS MCU [29]. Consequently, a TFET compact model covering its full regions is of the essence for circuit simulations. At this stage, an accurate and SPICE-friendly TFET capacitance model for all the operation regions is still missing in literature. The measured capacitance characteristic of TFET was reported [12], [13]. For capacitance modeling, a lookup table model was employed for TFET circuit simulations [14], [15] in early stage. Yang et al. [13] employed the modified capacitance expression of BSIM3 to model the measured TFET capacitance. A sort of TFET capacitance model [16], [17] used empirical expression to model the channel charge. Some physics-based models [18], [19], [20], [21], [22] calculate the terminal charge of TFET by surface-potential method and derive the terminal capacitance. These works focused on the charge components in the on-state BTBT operation region, and the approximate 100/0 drain/source partition [18] of channel charge was adopted. However, there was no discussion of capacitance modeling in ambipolar and forward p-i-n operation regions.