Complementary-Magnetization-Switching Perpendicular Spin-Orbit Torque Random-Access Memory Cell for High Read Performance

The read reliability of spin-transfer torque magnetic random-access memory (STT-MRAM) is greatly hindered by a low sensing margin as a result of a small tunneling magnetoresistance ratio. Although the new generation of perpendicular anisotropy spin-orbit torque (SOT)-MRAM offers faster access speed and a longer lifetime than STT-MRAM, its read performance has not improved or even deteriorated because of the additional resistance of the SOT channel in the read path. In this letter, we propose two novel cell structures of SOT-MRAM that consist of one/two transistors, two diodes, and two magnetic tunnel junctions (1T2D2MTJ/2T2D2MTJ) on a shared U-shaped antiferromagnet layer, enabling a self-referencing scheme. Thanks to the bent current channel, the opposite direction of the SOT current below the free layers can one-step switch different data states in compatibility with the existing fabrication process of SOT-MRAM. Combined with the 28 nm tech node and Verilog-A MTJ compact model, the simulation results show that our MRAM cell significantly improves the sensing margin and bit error rate over the conventional two transistors and one MTJ (2T1M) cell, which is expected to become a high read performance solution.

I. Introduction

To address the increasingly severe leakage challenge of conventional memories, spin-transfer torque magnetic random-access memory (STT-MRAM), an emerging type of nonvolatile memory (NVM), is increasingly recognized for its high write speed, near-zero static power dissipation, and almost unlimited read/write cycles [Bhatti 2017]. However, compared with other NVMs, the low tunneling magnetoresistance ratio (TMR) (≈100%–200%) makes it more difficult to distinguish the “1” and “0” states (e.g., resistive random-access memory can easily reach a switching ratio of 10 or more [Zahoor 2020]), which not only increases the design difficulty of the sensing circuit but also increases the verification bit of the error-correcting code circuit. Additionally, the inherent incubation delay, wide write time distribution, high write energy consumption, asymmetric write current, and the risk of oxide layer dielectric breakdown also obstruct its further development