Multiobjective Optimization for PSIJ Mitigation and Impedance Improvement Based on PCPS/DR-NSDE in Chiplet-Based 2.5-D Systems

The utilization of modular chiplets in interposer-based 2.5-D heterogeneous systems simplifies fabrication and design, however, it also introduces significant noise challenges. This article presents a collaborative jitter-aware optimization in 2.5-D integrated circuits (ICs), incorporating power supply induced jitter (PSIJ), system impedance, target impedance, and decoupling capacitors, based on the hybrid precomputation and prestorage/duplicate removal-nondominated sorting differential evolution (PCPS/DR-NSDE) algorithm. An automatic channel model algorithm and a uniform decoupling capacitor placement strategy are proposed to improve the design efficiency. Then, the system transfer impedance, simultaneous switch current, sensitivity function, and amplification factor are individually modeled, leading to the assembly and verification of the final PSIJ in the 2.5-D system. A precomputation and prestorage (PCPS) strategy is proposed to handle high-time-consuming modules in the objective function and a duplicate removal (DR) operation is added to improve algorithm performance. The proposed PCPS/DR-NSDE is faster than traditional algorithms and has optimal hypervolume and coverage-metric (C-metric) indicators. The procedures for further obtaining desired solutions in the Pareto front are discussed. The impact of practical constraints and target impedance is also analyzed. This work provides a collaborative optimization and analysis of jitter, noise, and impedance in 2.5-D systems.

I. Introduction

In recent years, conventional system-level System-on-Chip (SoC) design has involved fabricating multiple computing units, each tailored for different types of computing tasks, onto a single wafer through photolithography, pursuing “high integration.” However, with the failure of Moore’s Law and the demand for high-computing throughput and low-power consumption, the adoption of 3-D integrated circuits (ICs) has ensued [1], [2], [3], [4], which have some weaknesses, such as the significant overhead of silicon via [through-silicon via (TSV)], thermal dissipation, and elevated costs. Consequently, chiplet technology has been proposed. It decomposes the original SoC into multiple functional blocks with interconnection interfaces and selects appropriate processes for separate manufacturing. The adoption of interposer-based 2.5-D advanced packaging technology mitigates the need for all advanced processes for integrated manufacturing on the same wafer, significantly reducing dependence on advanced manufacturing processes.