CNTFET-based Design of Ternary Adders based on GDI Technique

The design of ternary adders based on the GDI approach employing Carbon Nanotube Field Effect Transistors (CNTFET) is presented in this study. Binary logic gates have always been the foundation of digital computing systems, but with increasing demand for high computational efficiency and low power consumption, the ternary logic is used. Ternary logic provides fewer interconnections, compact circuitry, and faster computations in advanced computing systems. The proposed design provides less power consumption, better speed, and less chip area than existing designs. The fundamental criterion for a VLSI system nowadays is low power consumption, which can be addressed by lowering the number of transistors on the device. As a result, the gates are designed using the Gate Diffusion Input (GDI) technique. Instead of using MOS, CNTFET is used as they have less power consumption and provide higher speed. Integrating all these advantages results in highly efficient computational logic like a half adder and a full adder. For the design purpose the Stanford CNTEFT model- Verilog A with 32nm technology and the tool for the simulation purpose Cadence Virtuoso is used.

I. Introduction

As the need for MOS transistor replacements in electronics has grown, the CNTFET has emerged as a strong contender thanks to its special abilities to deliver low OFF current characteristics, reduced power consumption, and improved performance [1]–[5]. Short channel effects on MOSFETs like Drain-Induced Barrier Lowering (DIBL), impact ionization, and surface scattering are becoming more prevalent as we approach the nanoscale [6] - [7]. The threshold voltage of CNTFETs is dependent on diameter, which gives them an additional benefit over MOSFETs. We can therefore obtain different thresholds by varying the diameter and chirality of CNTs.