Simple Algorithm for Mitigating Neutral Point Voltage Fluctuations(NPVF) in 3L-NPC inverter used for Solar Applications | IEEE Conference Publication | IEEE Xplore

Simple Algorithm for Mitigating Neutral Point Voltage Fluctuations(NPVF) in 3L-NPC inverter used for Solar Applications


Abstract:

This paper presents a simple algorithm for mitigating neutral point voltage fluctuations (NPVF) in a 3-level Neutral point clamped inverter (3L-NPCI) used for solar appli...Show More

Abstract:

This paper presents a simple algorithm for mitigating neutral point voltage fluctuations (NPVF) in a 3-level Neutral point clamped inverter (3L-NPCI) used for solar applications. The proposed algorithm does not require determining the direction of the neutral point current and hence by simply controlling the percentage of the P-type and N-type medium vectors applied in each switching cycle the NPVF of the mid-point can be controlled within limits. The algorithm can easily be implemented in the software and can be integrated with the SVPWM-based PWM technique. The NPVF of the mid- point of the DC link capacitor in a grid-tied 3L-NPCI is reduced without using costly bulk DC capacitors, additional hardware with switching circuits or passive elements. The selected PWM scheme utilizes both P-Type and N-Type vectors in each dwell time calculation which makes this algorithm simple to implement in the software. The effectiveness of the algorithm is further validated using simulation results on the 225 kW 3L-NPCI based grid-tied solar inverter.
Date of Conference: 17-20 December 2023
Date Added to IEEE Xplore: 31 January 2024
ISBN Information:
Conference Location: Trivandrum, India

I. Introduction

Many research efforts have been made to investigate and improve the power density of grid-tied centralized inverters for large PV systems. The multilevel topologies such as three-level Neutral point clamped inverter (3L-NPCI) and three-level T-type NPCI (3L-TNPCI) [1]-[3] have gained importance due to their advantages i.e. (a) lower switching and conduction losses, (b) Lower voltage stresses across the switches hence enabling the use of lower rating devices, and (c) Lower total harmonic distortion (THD) enabling the reduction in the weight, size of the passive filters employed for filtering purpose to meet the harmonic requirements as per the grid code.

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References

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