Area-Efficient VLSI Design for Fibonacci Q-matrix-based Cyber-Physical Systems using Canonical Signed Digit Recoding Methods with Modulo Reductions

Nowadays, cyber-physical systems (CPS) are used to integrate physical and software units and provide real-time, continuous, synchronous/asynchronous computations. The systems are useful in many applications. To provide security and privacy for CPS systems, a novel encryption/decryption for CPS based on Fibonacci Q-matrix was proposed by software implementations. However, as the values of parameters in encryption/decryption processes become large, the area costs become higher. To make this method suitable for very large scale integrated (VLSI) implementations, we used canonical signed digit (CSD) recoding methods to recode the parameters for encryption/decryption processes and reduce the number of partial products. The area costs were reduced, leading to area-efficient implementations. According to the analysis, we reduced the area by 40% with shorter delays in the encryption/decryption processes. The proposed method is useful for VLSI implementations for Fibonacci Q-matrix-based encryption/decryption schemes.

I. Introduction

The cyber-physical system (CPS) integrates physical and software and provides real-time, continuous, synchronous/asynchronous computations [1–5]. CPSs are applied to aerospace, defense systems, energy systems, healthcare, and transportation. To provide more security and privacy for CPS systems, a novel encryption/decryption for CPS based on Fibonacci Q-matrix has been proposed [7] by being implemented and coded in real CPS environments. The Fibonacci Q-matrix is generated using the values of n denoted as the complexity for encryption/decryption, and parameters are generated for the encryption/decryption matrix. The dimension of the encryption/decryption matrix is 2 by 2. The values of plaintext are partitioned into 4 entries and multiplied by the values of the denoted encryption matrix to generate cipher texts during encryption, and the cipher texts formed in a 2 by 2 matrix are multiplied by the decryption matrix to obtain the values of plaintext during decryption. The main computation bottleneck for encryption/decryption for the Fibonacci Q-matrix is multiplications as n becomes large. Thus, the multiplication operations become time-consuming with high area costs. To make this method suitable for very large scale integrated (VLSI) implementations while reducing the area and delay required for encryption/decryption, we used the canonical signed digit (CSD) recoding method for each entry in the encryption/decryption matrix. By CSD recoding, at least 40% area reduction was achieved with a shorter delay compared with the original method. Using the CSD recoding method, the area and delay were reduced significantly as the values for n becomes larger. In addition, in the decryption process, modulo reduction was applied to obtain more area reductions, too. By employing CSD recoding, we proposed area-efficient VLSI design architecture for Fibonacci Q-matrix-based cyber-physical schemes. The proposed hardware can be employed in cyber-physical schemes to achieve more area and delay-efficient security and privacy.