Contents Introduction
The operation of the Large Hadron Collider (LHC) at CERN demands sub-part-per-million (ppm) short-term stability of the currents in the superconducting dipole and quadrupole magnets. Within the digitally implemented current regulation loop, this performance is ensured by a dedicated high precision measurement chain that consists of direct current current transformers (DCCTs) and analog-to-digital converters (ADCs) [1]. A special ADC, the DS22 [2] was developed at CERN in the 1990s and deployed prior to the startup of the LHC in 2008. It was realized as a third-order Sigma-Delta topology and was built of discrete components, since integrated ADCs with sufficiently good performance were not available at the time. A more recent evaluation of DS22 is reported in [3].
The High Luminosity LHC (HL-LHC) project [4], due to start operation in 2029, aims at increasing the integrated luminosity at the Compact Muon Solenoid (CMS) and A Toroidal LHC Apparatus (ATLAS) detectors by an order of magnitude over ten years of operation. For that purpose, it will employ novel Nb3Sn based superconducting magnets with unprecedented requirements for short- and mid-term current stability. The new specifications were derived from the LHC operational performance, as well as from dedicated beam optics studies [5], [6], [7].
This work, which is an extension of the IEEE I2MTC proceedings paper [8], presents the metrological characterization of the HPM7177 digitizer conducted using the programmable Josephson voltage standard (PJVS) at PTB-Braunschweig.
Requirements
Table I shows a summary of the new Accuracy Class 0 requirements for power converters (PCs); hereby ppm refers to the rated value of the output current of the PC. All but the last requirement is defined for isothermal conditions. The first two parameters do not refer only to the measurement system, but also to the capabilities of the digital controller and the calibration infrastructure that was put in place for the LHC [1], [9].
The specifications are further subdivided into guidelines for the DCCT and the ADC; in this case ppm refers to the rated output voltage of the DCCT, 10 V, which is also the nominal full-scale input voltage of the ADC (henceforth 1 ppm = 10μV). Some specifications are not divided equally, as they are easier to be met by the ADC, allowing for less stringent DCCT requirements. Simple sums are used instead of rms-summation of the random quantities to ensure a safety margin. Another √2 margin exists for the noise-dominated parameters due to the redundancy of the measurement chain: in normal operation, the readings from two independent channels are averaged.
Design
A block diagram of the HPM7177 is shown in Fig. 1. Three functional blocks are highlighted and briefly described in Section III-A: ADC mezzanine containing all precision circuits, Section III-B: Digital logic and interfaces, and Section III-C: Temperature stabilization sub-system.
A. ADC Mezzanine
The digitizer is built around an integrated Sigma-Delta ADC—the AD7177–2 by Analog Devices. It was selected following a market study of high-resolution ADCs [10] and subsequent laboratory tests on selected candidates. The AD7177–2 was found to have the lowest intrinsic 1/f noise of all tested devices, in particular when its built-in buffers are disabled. Other characteristics, such as temperature drift and linearity, were found to be adequate for the application. It is worth noting that ADC specifications and research papers use full scale for the range between minimum and maximum digital codes whereas we use the definition common for voltmeters and other instruments. The HPM7177 digital codes correspond to the input-referred range from approximately −13 V to +13 V, while the nominal full-scale voltage is 10 V.
The required input signal range of ±10 V with certain over-range margin defined the need for attenuating the signal before the ADC chip. The attenuator front-end is realized as a symmetrical dual-branch fully differential circuit with buffered inputs and settable output common-mode voltage. The most important requirements for low broadband and low-frequency noise, as well as high linearity and low temperature drift, are met using auto-zero amplifiers and a metal foil resistor network with specified inter-element temperature coefficient (TC) matching of ≤1 ppm/°C [11], [12]. In a separately conducted study [13], this resistor network was found to have extremely low bias-dependent excess noise. An upper limit of the noise index of −70 dB ensures a negligible 1/f noise contribution in the present application. Another important feature of the fully differential attenuator is the high common-mode rejection ratio (CMRR) achieved by circuit symmetry and trimming.
The first prototypes of HPM7177 were built with the LTZ1000A buried Zener voltage reference. Subsequent versions employ a newer pin-compatible component—the ADR1000 [14]. The main advantage of using the ADR1000 in the present application is the improved low-frequency noise, which has lower device-to-device spread as well.
The raw reference voltages provided either by LTZ1000 or ADR1000 are too high to be used directly by the AD7177–2; therefore, they have to be translated down to approximately 5 V. The scaling is done using a second unit of the same metal foil resistor network used in the input attenuator [11]. Six elements (of two different values) are connected in series or in parallel to achieve a nominal division ratio of 1:1.41, while the remaining two elements are used for a gain-of-two amplifier to generate a fixed Uref × 2 signal for test purposes.
B. Digital Logic and Interfaces
The digital functionality of HPM7177 is implemented in a field-programmable gate array (FPGA). A CMOD A7–35T module from Digilent was selected. It contains a Xilinx Artix 7 FPGA, configuration flash memory, universal serial bus (USB)-to-JTAG interface, as well as other support circuits. The use of this module greatly simplifies the layout of the mainboard.
The FPGA module communicates with the AD7177–2 using the serial peripheral interface (SPI) translated to low-voltage differential signaling (LVDS) levels. This scheme minimizes parasitic coupling from the digital interface to sensitive analog circuits on the ADC mezzanine.
For current regulation, HPM7177 interfaces to the Function Generator Controller (FGC) [15], [16] through a plastic optical fiber interface. The digitizer outputs data packets at a fixed rate of 10 kSamples/s, synchronized to a pulse train sent from the controller. The baud rate of the universal asynchronous receiver-transmitter (UART) is 5 Mbit/s, and each data packet contains the raw 32-bit ADC conversion result, a 32-bit status word, and a cyclic redundancy check (CRC) checksum.
A galvanically isolated USB interface is also present in the digitizer. It is meant for debugging and production tests, but can be used for standalone readout as well.
C. Temperature Stabilization
All electronic components that contribute directly to the measurement accuracy were chosen for sub ppm/°C TC. However, the HL-LHC Class 0 requirements call for even lower guaranteed TC (see Table I).
Very low temperature drift is achieved in HPM7177 with the help of active temperature control. All sensitive circuits (ADC chip, input attenuator, and voltage reference) are contained in a small temperature-stabilized submodule. The ADC mezzanine board is placed inside a thermally isolating enclosure and its temperature is measured using a thin-film platinum temperature sensor (PT1000). The temperature-dependent resistance measurement is referenced to two fixed resistances of 1 kΩ and 1.5 kΩ, both realized within a single Z-foil SMNZ network [17]. The actuator is a Peltier element used either in heating or cooling mode. In all tests presented in this work, the temperature set point was 40 °C, and the control loop was implemented digitally using a proportional-integral (PI) algorithm.
Metrological Characterization
A characterization campaign was carried out at PTB-Braunschweig, in which two HPM7177 units were tested using the 10 V PJVS [18], [19]. Some results presented in this section are complemented with measurements carried out using equipment from the CERN Standards Laboratory maintained by the High Precision Measurements section.
A. Test Setup
A block diagram of the test setup is shown in Fig. 2.
The PJVS consists of three principal parts: 1) cryoprobe with a Josephson junction (JJ) array immersed in liquid helium; 2) bias current source; and 3) microwave synthesizer. The array consists of 69632 series-connected JJs, and the bias source provides current biasing of different groups of junctions to set the desired output voltage [19]. The microwave synthesizer receives a 10 MHz reference signal from the primary frequency standards at PTB and up-converts it to 70 GHz with a further possibility for fine-tuning with a resolution of 4 kHz (5.714 × 10-8).
The output voltage of the PJVS is given by the following equation:
\begin{equation*} U_{\textrm {PJVS}} = \frac {n M f} {K_{\mathrm {J}}} \tag{1}\end{equation*}
| n | =0 or ± 1 is the Shapiro step order; |
| M | is the number of biased junctions; |
| f | is the microwave frequency (nominally 70 GHz); and |
| KJ | =(2 e/h)=483597.8484 … × 109 HzV-1 is the Josephson constant (e being the elementary charge and h Planck’s constant). |
The stability of the PJVS voltage is directly determined by the frequency reference, which has a fractional stability better than 10−12. A practical limitation arises due to thermal electromotive force voltages (EMFs) in the wiring junctions. They are typically of the order of 10−7 V and tend to be stable after the initial settling, if the setup remains unperturbed. All of the reported measurements were taken after one full day of settling, following a period of over ten days during which the digitizers were powered but not connected to the PJVS.
A dedicated 19″ chassis was built specially for these tests. It housed two HPM7177 units together with two separate power supplies built using high-isolation dc-dc converters [20]. The inputs of the two digitizers were connected in parallel for most tests, so that both units measured the same signal coming from the PJVS cryoprobe. The interconnection was done using a low thermal EMF copper block, where the shields of the signal cables were also connected together and earthed at a single reference point. All powering and signal paths both within the PJVS system and the device under test (DUT) ensured high isolation at DC and up to higher frequencies, thus minimizing parasitic loop paths.
The readout system was built around a National Instruments PXIe chassis housing an embedded controller, FPGA module, and input-output (I/O) extension card with LVDS signaling. The bidirectional optical fiber signals were converted to LVDS levels using a custom-built interface card.
B. Broadband Noise
Previous measurements of the broadband noise floor away from zero (mid-scale) were limited by the intrinsic noise of the external source. To overcome this limitation, tests were carried out with internally generated voltages coupled through the input multiplexer (see Fig. 1), as well as external virtually noise-free voltages from the PJVS. The broadband noise at the PJVS output is deemed to be dominated by the series resistance in the output cables (<5 Ω), therefore at least two orders of magnitude below the noise floor of the digitizer. The spectral density of broadband noise was calculated with an FFT resolution of 0.1 Hz up to the Nyquist frequency fs/2=5kHz and with 100 averages per spectrum. Fig. 3 summarizes the results for the white noise floor from 0.1 Hz to 5 kHz. The error bars represent the expanded uncertainty of the mean at 99.7% confidence level (k = 3). To comply with the HL-LHC Accuracy Class 0 requirement of 0.5 ppm rms (see Table I), the mean white noise floor from 0.1 Hz to 500 Hz has to be lower than 223 nV Hz−1/2.
Both plots in Fig. 3 reveal a small dependence of the white noise floor on the input voltage level. However, since the internal nonzero test levels (approximately 4.7 V, 6.6 V, and 9.4 V) are derived from the voltage reference in HPM7177, their noise is partially correlated with the noise on the reference voltage provided to the ADC chip (approximately 4.7 V). This fact leads to the suppression of the correlated part, hence the apparent weaker dependence with respect to measurements with external voltages from the PJVS, where the total intrinsic noise of the digitizer is present.
C. Stability and Low-Frequency Noise
During the campaign at PTB, continuous measurements were taken at the PJVS voltage level nearest to 10 V with a total duration of over ten days. Time domain plots for both tested units are shown in Fig. 4 at a reduced data rate of 0.01 Samples/s. The lower subplot shows “12-h stability” as defined in the HL-LHC specifications (see Section II), evaluated with a sliding window. The environmental conditions in the laboratory during the measurement are shown in Appendix: temperature remained stable to within 0.5 °C and the variation of relative humidity was lower than 15%.
Stability at full scale measured with 9.99994118 V from the PJVS over more than ten days.
Fig. 5 compares the PJVS measurement of Unit A from Fig. 4 to data records of the same length obtained at CERN with 0 V (shorted inputs), as well as 10 V from a Fluke 732B voltage standard. The lighter colored lines show data at a rate of 1 Sample/s, while the solid black lines show the data further decimated to 0.01 Samples/s.
Time-domain plots of measurements taken at zero and full scale. The black data points result from further 100:1 decimation from the original data at 1 Sample/s.
The data records shown in Fig. 5 were used to calculate the spectral density of noise down to 10−4 Hz using the Welch method [21] with overlapping Hanning windows. The results are shown in Fig. 6, together with the HL-LHC Accuracy Class 0 guideline for “short-term stability” defined for the bandwidth of 10−3 – 10−1 Hz (see Table I). From the figure, we can extract a corner frequency of < 0.1 Hz. The PJVS does not contribute 1/f noise, so the increased level away from zero can be attributed entirely to the HPM7177. The white noise spectral density above the corner frequency is better emphasized in Fig. 3.
The overlapping Allan deviation was also calculated [22] for characteristic times up to 105s (> 27h). Fig. 7 shows the corresponding plots, which also includes guides to the eye corresponding to dominant contributions from white noise (τ-1/2), 1/f noise (τ0) or drift (τ1/2). The measurements at 0 V and 10 V from the PJVS are dominated by 1/f noise between 10 s and 3 h. The 1/f noise floor measured with the PJVS at full scale is approximately 7 × 10-8 V.
D. Linearity
The non-linearity of the tested digitizers was evaluated with stepwise ramps generated by the PJVS. Fig. 8 shows three plots for each unit, corresponding to different ramps as listed in Table II. The expanded type A uncertainty at k=3 was estimated for the steps near 10 V, where the noise contribution of the digitizer is the highest, so it represents the worst case over the tested range. The voltages from the PJVS are assumed to be perfect, and the three-point calibration removes the offset and gain errors, i.e., both at −10 V and ++10 V, for each plot. The plots do not overlap exactly because of the uncertainty of the calibrations, and also due to the large-step settling effect described in Section IV-E, since the ramps always started with a 0 V to −10 V transition.
The ramps that produced curves (B) and (C) were executed as single uninterrupted runs, while curve (A) was reconstructed from four separate measurement runs due to limitations in the PJVS control software.
The asymmetric shape of the non-linearity curve appears to be a feature of the ADC. Its positive section (0 V to +10 V referred to the digitizer input) has better unit-to-unit repeatability than the negative part (see [8, Fig. 4]). The measured non-linearity is better than the manufacturer-provided ADC specification, most likely because in HPM7177 the input range of ±10 V occupies only part of the ADC signal range, and this part is more linear than the full range.
An additional ramp test was carried out with single-junction steps and limited range from −1V to +1V. It confirmed that the sharp kink of approximately 0.1 ppm seen in the curves around 0 V does not originate from the PJVS or the data processing, but is also an internal feature of the DUT.
E. Settling to Large Voltage Steps
To study the settling behavior of HPM7177 with large steps, the PJVS was set to generate a repeating three-level waveform (−10 V, 0 V, +10 V) with dwell time of 300 s on each level. An overnight 18-h long record was obtained, which was then segmented and the ensemble averages calculated for each of the four transitions to increase the signal-to-noise ratio. The results are shown in Fig. 9, with baselines aligned to zero for the settled period after 200 s. The insets show zoom-ins of the first 20 s.
The measurements reveal a predominant gain settling mechanism, which is larger for steps in the negative direction (see curves (C) and (D) in Fig. 9). When returning to zero, the settling tails are significantly smaller in magnitude and shorter in time, as illustrated in the lower subplot. No hysteresis was observed in these measurements.
F. Resolving of Small Voltage Steps
The PJVS provides fundamentally stable voltages with fixed resolution equal to the voltage of one biased JJ, which is approximately 145 μV. However, there is another degree of freedom that allows for fine tuning of the output voltage by varying the 70 GHz microwave frequency. The setting resolution of the microwave synthesizer is 4 kHz, which corresponds to a voltage shift of 8.27 pV per junction when biased on the n = ± 1 Shapiro step [see eq. (1)].
At the nearest level to 10 V, the number of series-connected biased junctions is 69 085, resulting in steps of 571 nV. Thanks to its good low-frequency noise performance, HPM7177 is capable of resolving such steps when the output data rate is sufficiently reduced and broadband noise suppressed. At the level nearest to 1V (6909 junctions), it was necessary to program 40 kHz frequency steps to produce voltage steps with the same magnitude.
In these tests, the dwell time on each step is 11 s, and each measurement run comprises ten consecutive ramps. Fig. 10 shows the segmented and overlaid ramps, together with their ensemble averages shifted upward by two steps for clarity. The baseline was established at the start of each measurement, so it corrects for drift since the most recent calibration.
It can be seen in Fig. 10 that the peak excursions from the mean level on each step are comparable to the step spacing. The higher noise at 10 V with respect to 1V is also evident. To further explore these findings, histograms of the peak deviation for all ramps and steps were calculated and plotted in Fig. 11. The figure demonstrates directly the performance metric known as “peak-to-peak resolution,” “noise-free bits,” or “noise-free code resolution” [10]. At 1 Sample/s this metric exceeds 23 bits referred to 10 V (level spacing of 1.192 μV, thus 1/2 LSB = 596 nV) or 24 bits of the bipolar 20 V range, not taking into account the additional over-range margin. It should be noted that a further reduction of the data rate would lead to an improved figure, because the 1/f noise corner even at 10 V is below 0.1 Hz (see Fig. 6); however, in the present measurements the estimate is restricted by the step dwell time. Furthermore, unlike the usual “noise-free code resolution” given by ADC manufacturers, where noise is measured at zero and is scaled to the full range of digital codes, we provide a system figure that takes into account the noise contributions of the input stage and the voltage reference, thus resulting in a more conservative and realistic estimate.
G. Slow Linear Ramp Response
The requirements for stability and noise of the current provided by the PC refer to the flat top of the LHC cycle [5]. However, beams are present already before this state is reached, so the measurement chain must ensure smooth operation from beam injection through ramp-up to the flat top. Transients, sharp steps, or signal artifacts such as idle tones [2], [3] are undesirable, as they could lead to increased beam losses, or in the worst scenario to tripping of the PC and subsequent beam dump.
Tests with the PJVS confirmed the lack of major nonlinearitites or other artifacts through the full measurement range (see Section IV-D). To gain further confidence on the behavior of HPM7177 across the positive unipolar range under conditions similar to LHC operation, a test was conducted with a slow 20-min linear ramp. It was generated using the digital-to-analog converter (DAC) of a high-performance audio analyzer [23], with level spacing much smaller than in the PJVS tests where the steps were approximately 14.5 ppm. The discrete-time derivative (x[n]-x[n-1])/Δt was calculated for the full-rate data at 10 kSamples/s, as well as for ramps decimated by factors of 2, 10, 104, and 105.
The results are shown in Fig. 12. It is evident that the derivative of the full-rate ramp [curve (A)] in the middle subplot) is completely dominated by broadband noise, which is further enhanced by the differentiation. Even a modest reduction of the data rate lowers this noise significantly. For the ramps decimated by large factors [curves (D) and (E)] in the lowermost subplot), the plotted derivatives reveal the expected rate of 10 V / 1200s = 8.(3) mV/s without any visible features other than noise.
H. Long-Term Stability
The long-term stability of the digitizers will be followed via regular calibrations throughout the lifetime of HL-LHC. Extrapolations from limited-duration tests (e.g. Fig. 4, [8]) and specifications of the voltage reference [14] suggest that the target of 4 ppm/year should be easily reached once the devices pass the period of initial settling. In all prototype units tested so far, the same pattern of gain settling was observed, which is consistent with the settling of the ADR1000 voltage reference toward lower absolute values over a period of several months.
The absolute voltage reading of the two units tested at PTB was evaluated again one year later using a reference device from the CERN Standards Laboratory having recent calibration traceable to the Swiss Federal Institute of Metrology METAS. It should be noted that beside the transportation back from PTB, the HPM7177 crate was power-cycled multiple times over the year, so the conditions are not identical to the application environment in the HL-LHC. The results for offset and full-scale drift are given in Table III. For the offset measurement, the uncertainty is determined by the initial calibration at PTB, which is limited by the digitizer zero-scale noise at 1 s measurement time. The calibration uncertainty of the 10 V reference standard is taken into account for the uncertainty of the full-scale drift.
To study the long-term stability of non-linearity, the ramp measurement corresponding to curve (C) in Fig. 8 was also repeated at CERN one year after the test campaign at PTB. It was carried out using a pulse-width modulation (PWM)-based voltage calibrator and a group of five HP/Agilent 3458A digital voltmeters (DVMs). Fig. 13 shows that the shape of nonlinearity for the two tested units remains similar, with variations on the order of only 0.1 ppm, which is within the limits of measurement uncertainty. The given error bars for the CERN measurement are the expanded uncertainty (k = 3) containing both type A and type B components, the latter derived from DVM specifications under the assumption of uncorrelated nonlinearity of the five units.
Discussion
Prototype units of the new HPM7177 digitizer were produced at CERN. They were tested extensively and found to be compliant with the requirements for Accuracy Class 0 PCs in the HL-LHC project listed in Table I. The devices also qualify for the less demanding Accuracy Class 2 [6].
The advantages of Josephson-based voltage sources have been demonstrated already for decades in the context of characterization of high-performance digitizers and DVMs [18], [24], [25], [26], [27], [28]. The campaign at PTB-Braunschweig provided the ultimate validation of HPM7177 by overcoming the limitations of standard reference instruments. All tests were conducted without modifying the basic setup shown in Fig. 2, and the PJVS system showed robust and stable behavior without requiring any intervention over the entire three-week measurement campaign. Previous estimates of the broadband and low-frequency noise of the digitizer were improved near its full scale and throughout the measurement range using noise-free test voltages generated by the PJVS. The uncertainty in the measurement of nonlinearity was also reduced with respect to classical methods counting on the linearity of DVMs [3], [24], [29], Fig. 13. Measurements with small steps demonstrated directly the high equivalent resolution of the ADC at 1V and 10 V. The “noise-free code resolution” is a common and intuitive way to represent the intrinsic noise of oversampling digitizers, in which codes are the result of digital processing and rounding rather than actual decision levels of a hardware quantizer.
In terms of temperature drift, low-frequency noise, and short-term stability, HPM7177 not only surpasses commercial digitizers [26], but has characteristics comparable to or exceeding those of high-end DVMs [30], [31] and even buried Zener voltage standards [32]. For instance, the 1/f noise floor of HPM7177 measured at 10 V with the PJVS is approximately √2 lower than the combined noise measured with Fluke 732B (see Figs. 6 and 7), or in other words the low-frequency noise contributions of the digitizer and the Zener standard are nearly equal. It should be noted that in HPM7177, the 1/f noise floor is not fully determined by the ADR1000 voltage reference, but there is also a multiplicative noise contribution from the ADC chip. Together they result in a 1/f noise floor at full scale that is more than two times higher than at zero scale. This dependence is much stronger than for broadband noise, where the difference is on the order of few percent (see Fig. 3).
There are comfortable performance margins for many of the tested parameters that would ensure compliance of the series with the HL-LHC requirements. The most stringent requirements are for mid-term stability on the time scale of one LHC fill (12 h), as well as repeatability over ten fills (120 h) with cycling from zero to full scale. The former is fully determined by 1/f noise originating from the ADC chip and the voltage reference. The effect of ambient temperature variations is mitigated by the use of temperature-stabilized racks for the Accuracy Class 0 systems, together with the very low temperature dependence of HPM7177. All prototypes tested so far had thermal drifts at least a factor of four below the target of 0.2 ppm/°C; the results for four units were reported in [8]. “Fill-to-fill repeatability” is likely to be affected by component aging, particularly in the period of initial settling of the voltage reference [14] and other components recovering from stresses induced by soldering and mechanical assembly. There is no hysteresis associated with excursions of the input signal (see Section IV-E). Furthermore, in normal operation the powering of the units will be backed up by an uninterruptible power supply (UPS), thus avoiding power cycling and its associated thermal effects.
In the Accuracy Class 0 systems, the HPM7177 chassis will be placed in dedicated temperature-controlled and electromagnetic interference (EMI)-shielded racks together with the DCCT electronics. However, the digitizer will be used also in Accuracy Class 2 systems, where it would be integrated in the 2 kA PC racks. Good EMI immunity is needed for this potentially noisy environment. Earlier results from electromagnetic compatibility tests showed low sensitivity to common disturbances, with reversible loss of measurement accuracy being the worst effect [8]. Further tests were carried out both at CERN and externally to ensure compliance with IEC/EN 61000 for emissions and susceptibility according to the levels specified for industrial environments. Integration tests with the new PCs and magnets will be performed at the IT String test facility [4] before the launch of HL-LHC, with the aim to validate the complete inner triplet powering systems.
ACKNOWLEDGMENT
The authors are grateful for the technical support provided by Vishay Precision Group and Analog Devices. The project documentation was prepared with the invaluable help of the CERN Design Bureau. We thank the CERN Electronics Assembly Workshop for building the prototype units, as well as Greg Hudson for providing a voltage standard with traceable calibration. Last but not least, we are grateful to John R. Pickering of Metron Designs for the fruitful discussions and particularly for the help with the ADR1000 voltage reference. PTB gratefully acknowledges the support by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) under Germany’s Excellence Strategy—EXC-2123 QuantumFrontiers—390837967.
AppendixLaboratory Environmental Conditions During Stability Tests
Laboratory Environmental Conditions During Stability Tests
During the three-week test campaign at PTB, the environment in the laboratory was monitored using portable loggers (type EasyLog EL-SIE-6+). The results plotted in Fig. 14 for the same time frame as the stability tests (Section IV-C) show the temperature and relative humidity close to the measurement setup, but sufficiently far away to be unaffected by heating from the PJVS controls or the DUT. The small ambient temperature fluctuations were traced to air movement in the laboratory when the Faraday cage door was left open for longer periods of time. Atmospheric pressure data for Braunschweig was provided by PTB [33].
Environmental variables in the laboratory during the mid-term stability test conducted at PTB-Braunschweig.