Look-up Table Size Reduction Strategy for Synchronous Optimal Pulse Width Modulation

Synchronous optimal pulse width modulation (SOPWM) offers low current total harmonic distortion (THD) at lower switching-to-fundamental frequency ratios. However, the SOPWM method requires a large amount of memory space from the microcontroller to achieve its best performance due to high-resolution pre-optimized optimal switching angles (OSAs), which is one of the major drawbacks of the SOPWM method. To address this drawback, this paper proposes a new strategy to reduce the look-up table size of OSAs in the SOPWM by generating new switching angles with few points from the original OSAs while ensuring the new switching angles error under desired range. The influence of optimal switching angle error on the voltage, current THD performance, and modulation index are also presented. Experimental and simulation results are provided to demonstrate the effectiveness of the proposed method.

I. Introduction

Synchronous optimal pulse width modulation (SOPWM) is a well-known modulation strategy for high-power and high-speed AC drives thanks to its inherent ability to provide a low total harmonic distortion (THD) at lower switching frequencies compared to other conventional PWM methods [1], [2]. Nonetheless, the applicability of SOPWM is still limited to medium voltage high-power applications, such as grid [3], industry [4], and railway [5], due to its poor dynamic performance and high-memory space requirement [6]. Although many researchers have successfully tackled the poor dynamic performance of SOPWM [7]-[9], the reduction of memory space requirements for the microcontrollers has not been addressed in the literature.