Abstract:
The development of SiP chips has driven the lightweight trend in electronics, but it also brings new reliability issues, especially package delamination caused by compoun...Show MoreMetadata
Abstract:
The development of SiP chips has driven the lightweight trend in electronics, but it also brings new reliability issues, especially package delamination caused by compound stress. This paper proposes a method for predicting the layered lifetime of SiP chip packaging based on physics-of-failure model. Taking an energy SiP module and its key components as an example, this paper analyzes the mechanism and influencing factors of package layering failure in different parts of SiP chip during reflow welding process and use. Through physics-of-failure model, the life of SiP chip in packaging layering process and reflow welding process is predicted. This research is of great significance for identifying weak points in SiP chip and the improvement of the design method.
Date of Conference: 20-23 October 2023
Date Added to IEEE Xplore: 11 December 2023
ISBN Information:
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