Optimized Pulse Patterns With Bounded Semiconductor Losses

This article proposes the computation of three-level optimized pulse patterns (OPPs) that achieve not only low harmonic load current distortions (load-friendly operation) but also low semiconductor losses (converter-friendly operation). To this end, the conduction and switching losses are modeled as a function of the OPP switching angles and the amplitude and phase of the converter current. By minimizing the current harmonics subject to an inequality constraint on the semiconductor losses, OPPs are derived that achieve minimal current distortions with a guaranteed upper bound on the semiconductor losses, thus ensuring the safe operation of the semiconductor switches within their thermal limits. Detailed numerical results for a medium-voltage system consisting of a neutral-point-clamped converter and an inductive load verify the benefits of this approach.

I. Introduction

Optimized pulse patterns (OPPs) are a specific pulsewidth modulation (PWM) method in which the switching signal is computed offline and stored in a look-up table. Unlike selective harmonic elimination [1], [2], OPPs require formulating and solving a mathematical optimization problem [3]. Traditionally, for a given number of switching angles, the current distortions have been minimized [4]; this, in turn, ensures minimal harmonic losses in the load and achieves load-friendly operation. The influence of the commutated current on the semiconductor switching losses, however, is ignored. Therefore, the semiconductor losses are limited only indirectly by operating at a fixed switching frequency.