First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology

With a novel laminated well isolation technology for complementary tunnel FET (TFET) devices, this work experimentally demonstrates the first bulk Si TFET-based circuits and hybrid TFET-CMOS circuits based on a 300mm CMOS foundry platform. By utilizing the proposed DTCO workflow, the designed novel laminated isolation well for bulk TFET can successfully suppress the parasitic leakage current between adjacent TFET devices without area penalty. Both all TFET-based logic gates and SRAM cells are experimentally demonstrated and verified, indicating the validity of proposed well isolation technology. Moreover, benefiting from the proposed monolithic integration process with CMOS, there are no parasitic leakage current paths between adjacent TFET and MOSFET, enabling the first experimental demonstration of hybrid TFET-CMOS circuits including logic gates and 5-stage ring oscillator (RO). This work promotes the realization of high-energy-efficient and large-scale circuits based on TFET-CMOS hybrid foundry platform towards power- and cost-constraint AIoT applications.

I. Introduction

Tunnel FET (TFET) has already demonstrated its superiority in terms of power consumption among emerging device technologies while suffering from the fundamental low on-state current (I_ON) issue [1]. Recently, co-integrated with baseline CMOS technology in 12-inch foundry platform, the novel complementary n- and p-type dopant-segregated TFET (C-DS-TFET) devices proposed in our previous work [2] have experimentally demonstrated record I_ON/I_OFF ratio among TFETs by industry-manufacturers without CMOS device performance penalty. However, the experimental demonstration of TFET-based circuits is extremely scarce, except a few inverter studies based on nanowire TFET structures [3]. So far, there is no experimental demonstration of TFET-CMOS hybrid circuits based on foundry platform. According to our previous work [4], for TFETs on CMOS foundry platform, heavily-doped sources or drains from adjacent bulk Si-based TFETs may induce parasitic leakage paths through substrate, leading to abnormal functionality and increased static power consumption in TFET-based circuits. For high-energy-efficient and large-scale circuit application, this work proposes a laminated well technology to solve the electrical isolation requirement between neighboring devices without area penalty. Based on this solution, we experimentally demonstrated the first bulk TFET-based circuits and TFET-CMOS hybrid circuits on the standard CMOS foundry platform.