Prospective Phase Frequency Detector Design Architectures for RF Transceiver Applications

One of the essential components of phase-locked loop (PLL) circuits is the phase frequency detector (PFD). PFD generates an error output signal whose phase difference between the phases of the feedback clock and the reference clock is proportionate. PFDs are mostly utilized in demodulators, motor control, radar, and communications systems, servo-mechanisms, and mobile communication systems. While designing a PFD blind zone, power consumption and operational frequency must be considered cautiously for better performance. In this study, a detailed analysis of various designs of PFDs is presented and analyzed for various applications. This may help researchers or designers from academies and industrial sectors choose a suitable device topology for RF transceiver applications.

I. Introduction

Many communication systems, including PLL, digital microwave radio (DMR), alias-locked loop (ALL), and clock-data recovery (CDR), included PFDs. PLL has remained a potent building element for many years, and in PLL systems [1] .