A Cost-Effective Ku-Band Phased Array in Package Integrating Multi-Independent CMOS Transceivers With On-Chip Antennas

A low-cost and integration-efficient Ku-band phased array is demonstrated for satellite communication, which is package integrated with four independent 180-nm CMOS transceivers (TRXs) with ON-chip antennas. To improve the integration of phased-array beamformer while considering the cost, a cost-effective packaging technique combining ON-chip and printed circuit board (PCB) is proposed. In addition, an OFF-chip guard ring array is introduced to further optimize the gain and sidelobe suppression level. The designed CMOS TRX integrated circuit (IC) achieves a measured maximum gain of 17.6 dB with a 3-dB bandwidth of 15.5–18 GHz in the transmitter (TX) mode. The receiver (RX) mode realizes a peak gain of 19.2 dB at 16.5 GHz. With the help of the proposed techniques, the packaged four-element phased array demonstrates a measured beam steering range of ±32°. It provides important guiding significance for the design of the phased array with high integration, superior performance, and low cost operating in lower frequencies.

I. Introduction

Phased-array technique has the capability of beamforming, which contributes to enhance the effective isotropic radiated power (EIRP) and thus improve the service coverage. It has been widely used in wireless communications and radar applications [1], [2], [3]. For large-scale phased-array transceiver (TRX) design, silicon-based process is preferred due to its low cost and easy integration with digital circuits [4], [5], [6], [7], [8]. Several silicon-based phased-array beamformers with integrated antenna array have been reported over the recent years [9], [10], [11], [12], [13], [14], [15], [16]. In general, there are two dominant antenna integration methods to build large-scale arrays, one way is OFF-chip package integration [9], [10], [11], [12], [13], and the other is ON-chip [14], [15], [16]. In the OFF-chip integration form [Fig. 1(a)], the antenna array is manufactured on the printed circuit board (PCB), featuring a high gain. However, it will inevitably introduce the interconnect loss between the silicon beamformer chip and antennas, which deteriorates the power strength and noise figure (NF). Worse still, interconnects with different lengths will introduce additional amplitude and phase errors between different channels. In addition, it requires an additional high-performance multilayer PCB to achieve the better antenna packaging, which not only increases the design cost but also requires careful design of packaging wiring and matching circuits. Based on the ON-chip integration method [Fig. 1(b)], the antenna elements are directly fabricated on the chip, which first avoids the interconnect between the chip and antennas by wire bonding, realizing high integration. On the other hand, it greatly reduces the phase and gain differences between channels. Nevertheless, this integration method will not be preferred for phased array operating in lower frequencies. To mitigate the coupling effect between ON-chip antennas, the spacing between two adjacent antennas needs to be kept at about half the wavelength (/2), which will consume a significant amount of chip area. Concerning the required performance, integration, and cost of phased array working at lower frequencies, advanced packaging techniques will be necessary. Fig. 1.

Block diagram of the phased-array TRX with (a) OFF-chip antenna package integration, (b) ON-chip antenna package integration, and (c) ON-chip and OFF-chip combining antenna package integration.