I. Introduction
Transistors based on III–V semiconductors have unique advantages in terms of bandwidth and power-handling capabilities due to their higher low-field mobilities and larger bandgap compared to silicon. As outlined in detail in Part I [1] of this article, III–V double heterojunction bipolar transistor (DHBT) process technology development and applications could benefit tremendously from TCAD tools that offer both sufficient accuracy and reasonable computation time [2], [3], [4]. The goal of this work (including Part I [1]) is to demonstrate that these requirements can be met by the combination of a Boltzmann transport equation (BTE) solver and a two-valley augmented drift-diffusion (aDD) solver, both have been described in detail in Part I [1].