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A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router | IEEE Journals & Magazine | IEEE Xplore

A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router


Abstract:

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi- or many-core System-on-Chip...Show More

Abstract:

Network-on-chip (NoC) has played a vital role in enabling high-speed and energy-efficient data communication among different cores in a multi- or many-core System-on-Chip (SoC). To mitigate the pessimistic timing margin reversed for severe process, voltage, and temperature (PVT) variations, we presented a wide supply voltage range router with a novel error detection and correction (EDAC) technique adopted in its latch-based pipeline for high energy efficiency. Especially, a unified clock-gated error correction scheme is presented to address dynamic timing errors under PVT variations and functional pipeline stalls when occurring allocation failure (packet fails to obtain an output port) or flow control (the next router stalls the current packet transmitting) in one cycle. Moreover, a latch-based pipeline structure with three non-overlapped clocks is adopted to further reduce the short-path padding overhead, which is significantly increased in the ultra-low voltage (ULV) regime. Consequently, we prototyped a 2\times2\,\,2\text{D} mesh NoC test chip with 28-nm CMOS technology. Compared with the margined baseline with a 10% VDD drop, measurement results show that the proposed router enables 1.4\times , 32.4%, and 7.5% improvements in frequency, energy, and area, respectively. Furthermore, the proposed techniques can reduce packet loss by 200\times and increase throughput by 19.9% for the NoC at 0.4 V, 25 °C.
Page(s): 3787 - 3791
Date of Publication: 23 June 2023

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I. Introduction

High-performance and energy-efficient system-on-a-chip (SoC) with tens to even hundreds of building blocks have gained a large amount of attention for emerging applications such as autonomous vehicles, drones, and robots. In such an architecture, network-on-chip (NoC) plays a key role to enable high-speed and energy-efficient data communication among blocks. As a result, the NoC may occupy up to 36% of the SoC power consumption [1]. To improve the energy-efficiency, dynamic voltage and frequency scaling (DVFS), adaptive clocking, timing resilient circuits design, and ultra-low voltage (ULV) operation techniques are widely adopted [2], [3]. However, when an NoC works in the ULV regime, it will exhibit severe delay variability across process, voltage, and temperature (PVT) variations, requiring a large amount of timing margin as a guard band. As a result, a large portion of the energy benefit in the ULV regime will be undermined.

References

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