An embedded DRAM technology on SOI/bulk hybrid substrate formed with SEG process for high-end SOC application

A highly manufacturable embedded DRAM technology in SOI (Silicon On Insulator) has been developed for high-end SOC (System On a Chip). Partial etching of SOI/BOX (Buried OXide) layers and SEG (Selective Epitaxial Growth) processes simply transform an SOI wafer into a high quality SOI/bulk hybrid substrate wafer, which has both SOI substrate regions and bulk epitaxial Si regions. DRAM macros developed for the bulk can be introduced in SOI without any modification of the design and process, resulting in stable DRAM operation freed from floating-body effects. Fabrication of 1 Mb ADMs (Array Diagnostic Monitors) on the hybrid substrate wafer with the 0.18 /spl mu/m embedded DRAM process has attained all-bits-functional yield of 90%. Moreover, excellent data retention characteristics, by no means inferior to those for a bulk wafer, were obtained in SOI for the first time. The proposed methodology is attractive for SOI SOC, where high band width with low power consumption due to DRAM-embedding as well as high-speed/low-power circuit performance of SOI logic can be enjoyed.

Introduction

Recently, demands for the embedded DRAM have been increasing rapidly, which brings about high bandwidth between memory and logic with low power consumption and reduced chip size [1]. On the other hand, SOI logic is becoming the mainstream for high-end or low power applications. Therefore, an SOI embedded DRAM will be general demands in near future.