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Comparisons between electrical and optical interconnects for on-chip signaling | IEEE Conference Publication | IEEE Xplore

Comparisons between electrical and optical interconnects for on-chip signaling


Abstract:

We present a comparison between electrical wires driven by repeaters and optical interconnects from both delay and power perspective. This involved properly modeling the ...Show More

Abstract:

We present a comparison between electrical wires driven by repeaters and optical interconnects from both delay and power perspective. This involved properly modeling the power and delay of each component in an optical signaling system as well as repeated wires. We show that it is favorable to switch to optical interconnects for global signaling, on both power and delay account, for long wires. Whereas, shorter wires favor an electrical operation on lower power grounds.
Date of Conference: 05-05 June 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7216-6
Conference Location: Burlingame, CA, USA

Introduction

The scaling paradigm adopted by semiconductor industry, while conducive to devices, severely degrades interconnect performance. On-chip optical interconnects presents a possible solution. While, the usefulness of optics in chip to chip communication is becoming clearer, there exists a considerable ambiguity in its utility in high performance on-chip applications. In this work, we address the optical system specifically for global signaling application. We first comprehensively model both optical and electrical links and subsequently compare their performance in the light of the two most important figures of merit: delay and power consumption. ITRS'99 parameters were used for modeling [1]. Fig. 1 shows a schematic of an optical signaling system consisting of the transmitter, the transmission medium (waveguide) and the receiver, and the best possible electrical signaling system with periodic repeaters to reduce delay. In this work the optical receiver is taken to be the popular transimpedance front-end design with subsequent gain stages to achieve CMOS level signaling [2].

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References

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