An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications

The proposed 8T Non-Volatile SRAM (NVSRAM) is designed to be resistant to power analysis (PA) attacks and is suitable for in-memory computing (IMC) applications. Our design uses a two-phase write operation instead of the traditional single-phase write operation, which reduces the correlation between stored data and power consumption during writing and provides resilience against PA attacks. It provides a mean energy difference (MED) of 5aJ, which is $1000\times $ less compared to available 6T SRAM cells. The proposed cell also utilizes a common Spin transfer torque (STT) current for both magnetic tunnel junctions (MTJs), which results in more energy efficient and faster store operations. The store operation becomes $2\times $ more energy efficient and $3\times $ faster compared to the available state of the art NVSRAM Cells. The Symmetrical structure of proposed cell and two stage store/restore operation provide PA attack resiliency during store and restore mode of NVSRAM. Additionally, the proposed cell performs IMC for XNOR computation by collocating the weights and activations stored in the same bit cell.

I. Introduction

SRAM cells are one of the preferred on-chip memory modules in processor architectures (Von Neumann and in-memory computing (IMC) architecture) owing to their high-speed operation. SRAM modules offer numerous benefits, such as high speed, low dynamic power, and reliability, for a wide range of applications. However, because of their volatile nature, these memory modules face the challenge of static power loss during the idle and hold modes of operation [1], [2]. One of the promising solutions might be Non-Volatile SRAM (NVSRAM) cell, which eliminates static power loss by storing data within the bit cell in a non-volatile device. NVSRAMs store data present on the Q & Qbar nodes of cross-coupled inverter in the non-volatile (NV) devices during standby/idle mode. The data stored in NV devices during standby/idle mode results in zero static power loss. When power is restored for the read/write mode operation, the data stored in the NV devices are restored back to the Q & Qbar nodes. In addition to the store and restore operations, NVSRAM works same as the SRAM cell during the conventional mode of operation and performs read and write operations. Recent research and developments in NVSRAM cells suggest that the incorporation of MTJs as NV cells improves the overall performance of memory modules [3], [4].