SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks

Spiking neural networks (SNNs) are an active research domain toward energy-efficient machine intelligence. Compared to conventional artificial neural networks (ANNs), SNNs use temporal spike data and bio-plausible neuronal activation functions such as leaky-integrate fire/integrate fire (LIF/IF) for data processing. However, SNNs incur significant dot-product operations causing high memory and computation overhead in standard von-Neumann computing platforms. To this end, in-memory computing (IMC) architectures have been proposed to alleviate the “memory-wall bottleneck” prevalent in von-Neumann architectures. Although recent works have proposed IMC-based SNN hardware accelerators, the following key implementation aspects have been overlooked: 1) the adverse effects of crossbar nonideality on SNN performance due to repeated analog dot-product operations over multiple time-steps and 2) hardware overheads of essential SNN-specific components, such as the LIF/IF and data communication modules. To this end, we propose SpikeSim, a tool that can perform realistic performance, energy, latency and area evaluation of IMC-mapped SNNs. SpikeSim consists of a practical monolithic IMC architecture called SpikeFlow for mapping SNNs. Additionally, the nonideality computation engine (NICE) and energy–latency–area (ELA) engine performs hardware-realistic evaluation of SpikeFlow-mapped SNNs. Based on 65nm CMOS implementation and experiments on CIFAR10, CIFAR100 and TinyImagenet datasets, we find that the LIF/IF neuronal module has significant area contribution $(>11\%$ of the total hardware area). To this end, we propose SNN topological modifications that leads to $1.24\times $ and $10\times $ reduction in the neuronal module’s area and the overall energy-delay-product value, respectively. Furthermore, in this work, we perform a holistic comparison between IMC implemented ANN and SNNs and conclude that lower number of time-steps are the key to achieve higher throughput and energy-efficiency for SNNs compared to 4-bit ANNs. The code repository for the SpikeSim tool is available at Github link.

I. Introduction

In the last decade, spiking neural networks (SNNs) have gained significant attention in the context of energy-efficient machine intelligence [1]. SNNs encode input data information with discrete binary spikes over multiple time-steps making them highly suitable for asynchronous event-driven input processing applications [2], [3]. Recent works have proposed full-scale general-purpose von-Neumann architectures leveraging the temporal processing property of SNNs [4], [5]. Other works, such as [6] and [7] have proposed novel dataflow to minimize the hardware overhead in von-Neumann implementation of SNNs. However, SNNs like conventional artificial neural networks (ANNs) entail significant dot-product operations leading to high memory and energy overhead when implemented on traditional von-Neumann architectures (due to the “memory wall bottleneck”) [8], [9]. To this end, analog in-memory computing (IMC) architectures [10], [11], [12] have been proposed to perform analog dot-product or multiply-and-accumulate (MAC) operations to achieve high memory bandwidth and compute parallelism, thereby overcoming the “memory wall bottleneck.”