Modification of Dynamic Logic Circuit Design Technique for Minimizing Leakage Current and Propagation Delay

This paper is based on the OR logic operation’s small discharging current and transmission time delay dynamic logic circuit configuration method. In terms of static logic circuits, it require a larger number of transistors and consume a massive amount of power. However, high-speed dynamic logic circuits consume less power due to their lower number of transistors. But, it has an issue with the evaluation phase where current gets leaked from the dynamic node due to sub-threshold leakage. In this paper, we have shown a new dynamic logic circuit design procedure for reducing leakage current from the dynamic node by using delay component, stacking effect, current mirror circuit with footed nmos, and a keeper circuit with the keeper device. The suggested system is analyzed in LTSpice with 45nm CMOS predictive technology model and compared with the previous research to demonstrate validity. The simulation study demonstrates power savings relative to traditional architecture and verifies the suggested strategy. This circuit could be used for designing low power consuming and delay systems for wide fan-in and can be useful for cascading several stages.

I. Introduction

In CMOS circuits, logic functions are achieved by switching the current flow channels of MOSFETs. The most common CMOS circuits are static logic gates because they are simple to construct, have controlled features, and have a high noise immunity [1]. The fundamental framework for static logic is provided by the CMOS inverter. A full-rail output voltage swing and completely dynamic power dissipation are produced when nMOS and pMOS transistors are used in complementary fashion. Whereas, clocked pMOS pullup is used by dynamic gates. Precharge and Evaluate are the two modes of operation used to create the logic function or logic gate. Here, fewer transistors (N+2) are needed than in static CMOS circuits (2N), yet the circuit still requires less transistors per ratio than static [2] [3].