Design and implementation of a turbo decoder for 3G W-CDMA systems

This paper presents the design and hardware implementation of a log-MAP turbo decoder used in the third generation (3G) mobile communication W-CDMA systems. The decoding algorithm is highly data dominated and needs many memories for data storing. The memory requirements are systematically investigated and optimized from two aspects: (1) an alternative called state metric difference-storing method is proposed to save the forward state metric (/spl alpha/) and the backward state metric (/spl beta/) memory up to 1/3; (2) the interleaver address memory is reduced by repeating the address calculation at each iteration. The experimental results on an FPGA prototype of the decoder show that it supports 2Mbits/s data rate with five iterations, and for code blocks of more than 2000, a bit error rate (BER) of 10/sup -6/-10/sup -7/ is achieved at E/sub b//N/sub o/=1.0 dB after only five iterations.

I. Introduction

Since turbo codes, which are composed of parallel concatenated convolutional codes (PCCCs), were presented by Berrou et al. in 1993 [1], they had received a lot of interest in the coding community due to their outstanding error correcting performance, which appears to be close the theoretical limit predicted by Shannon [2]. Turbo codes as a channel coding technology have extensive applications in particular in error-prone environments, such as wireless personal communications [3] [4] and deep-space communications [5] [6]. They have also been adopted as channel coding for data transmission in the generation mobile communication standards: i.e. W-CDMA (Wideband Code Division Multiple Access), cdma2000 and TD-SCOMA.