Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers

Weighted round-robin (WRR) arbitration provides global fairness in networks-on-chip (NoCs) as opposed to the commonly used round-robin and priority-based arbitration techniques. However, the large number of weights explodes the design space and exacerbates performance (latency-throughput) tuning. Therefore, fast and accurate performance analysis techniques for NoCs are crucial for accelerating design space exploration and accurate pre-silicon evaluation. This article presents the first comprehensive performance analysis technique for NoCs with WRR arbitration and finite buffers. It can handle bursty traffic and is scalable to large NoC sizes. The proposed technique first estimates the probability that a queue is full and uses this result to compute the modified service time and queuing delay. Thorough experimental evaluations with synthetic traffic and real applications show that the proposed analytical model is always more than 10% accurate compared to cycle-accurate simulations. Moreover, the proposed performance analysis technique is five orders of magnitude faster than cycle-accurate simulations for a $16\times16$ mesh NoC.

I. Introduction

Massive industrial and academic research efforts aim to continuously enhance the performance and energy efficiency of many-core processors. Networks-on-chip (NoCs) are the standard choice for on-chip communication in these processors used in servers [1], [2], [3], [4] and personal computers [5] executing various applications, including deep learning [6], [7], [8], [9], [10]. Since modern applications exhibit immense data communication between processing cores (e.g., 2.7 TB for a graph processing application), the NoC performance is critical to overall system performance and pre-silicon evaluation [6], [7]. Although cycle-accurate NoC simulations provide accurate analysis, they consume up to 60% of the full-system simulation time [11]. Analytical modeling for NoC performance is a promising alternative to cycle-accurate simulation to speed-up performance evaluation. Besides providing fast NoC performance estimates, analytical models must be accurate and general enough to capture important aspects of industrial many-core processors used in different generations.