A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs

Existing methods used for the clock distribution of multiple dies employ a balanced tree structure to minimize the impact of the within-die process and loading variations. No topology for die-to-die clock skew compensation of more than two dies has been presented yet. This article presents a novel die-to-die clock skew compensation topology to address these limitations. Unlike existing designs, the proposed topology does not need a phase detector (hence, no dead zone); it only requires one through-silicon via (TSV) to connect a pair of dies and one digitally controlled delay line (DCDL) in each die; thus, there is no skew from extra TSVs and DCDLs. Accordingly, the system has a small chip area and low lock time. The postsynthesis of this work was accomplished in a 65-nm CMOS process. The performance of our design was evaluated theoretically and practically in terms of mismatch/finite resolution of delay lines, buffer mismatch, and TSV delay. Under identical conditions, the residual skew of the proposed design was as low as 13 ps at 1 GHz. This study is the first to obtain the solution for die-to-die clock synchronization of multiple dies (more than two dies) in a three-dimensional (3-D) integrated circuit, while other systems can only support two dies.

I. Introduction

Moore’s law states that the number of transistors on an integrated circuit (IC) doubles every two years; this has mostly been true since the first IC was introduced. However, it has become increasingly difficult to reduce the size of transistors. Eventually, transistors will become too small to be further reduced, and their physical constraints will essentially limit the growth of transistor density on chips. To deal with this limitation, researchers have focused on stacking multiple dies on top of each other, known as three-dimensional (3-D)-IC; this topology can significantly increase the number of transistors contained in a package, since the number of all components is effectively multiplied in each chip. Bonding wires have also been utilized to connect these two-dimensional (2-D) fabricated dies. However, a recent die-to-die interconnection known as through-silicon via (TSV) has attracted considerable attention because of its high density, low latency, and power reduction capability [1]. In addition, TSVs can be placed anywhere on dies, increasing the number of I/Os while significantly reducing the wire length between dies. However, distributing clocks in 3-D-ICs with TSVs is a significant challenge because of the following reasons: 1) the delay across TSVs leads to critical clock skew among dies, which can accumulate every time a clock signal transmits through TSVs and 2) TSV delay is susceptible to process, voltage, and temperature (PVT) variations [1], [2], [3], [4], [5], [6], [7], [8], [9], thus the assumption of fixed TSV delay is not practical in the design. Consequently, the propagation delay across the TSV exhibits very large delay variations, and an approach that tolerates any unanticipated TSV delay variations for inter-die clock distribution is needed.