Design of CPO Daughter Board with FPGA and 25-Gbaud × 16-Channel Ultra-Compact Optical Transceivers

We design a CPO daughter board on which 32 ultra-compact transceivers are mounted with an FPGA. The high-speed differential transmission lines are designed with the aid of electro-magnetic simulations. Eye diagrams are simulated by high-speed circuit simulations. Measured 25-Gbaud NRZ eye diagrams have a good agreement with the simulated results. Electrical crosstalk was suppressed to −30 dB and lower. The simulated eye diagrams have no degradation even activating the aggressors.

I. Introduction

The next generation mobile communication system (i.e., Beyond 5G) has been expected to achieve enhanced mobile broadband (eMBB), ultra reliable low latency communications (URLLC), and massive machine type communications (mMTC). To realize these functionalities, network switch servers need to increase the bandwidth, save the power comsuption, and realize the low latency. The bandwidth of switch application specific integrated circuit (ASIC) has a trend of doubled in two years. Following this trend, Broadcom announced starting the delivery of 51.2 Tb/s Ethernet switch chip (Tomahawk 5®) on August 2022 [1]. Since it is difficult for the existing pluggable optical transceivers employing small form factors (SFFs) placed at a front panel to support the bandwidth of ≥51.2 Tb/s and save the link power, network switch servers need to adopt a new server architecture using Co-Packaged Optics (CPO).