I. Introduction
Low power design is required to reduce power consumption in high-end systems with high integration density. The low power method should be utilized throughout the design process, from system to process level, to optimize power dissipation [1]. Chips with high clock frequencies are being created due to increasing chip density and operation speed [2]. Even though the number of logic bits is the same, many valued logics may convey exponentially more data/information than binary logic [3] which is based on vertical channel FinFET with larger effective channel width, higher drive current capabilities in addition suppressed short channel effect at lower technology nodes (<22nm). Modern image and video processing systems, as well as DSP chips and microprocessors, need a high number of arithmetic operations [4]. Addition and subtraction are among the most fundamental mathematical operations, and they are extensively utilized in contemporary computer applications [5]. Soft errors in SRAMs are becoming more frequent as CMOS technology advances [6]. The requirement for transistor technology changes raises the chance of error [5]. Where data is absent, ternary logic gates are needed. As a result, multi-valued logic is presently being researched to reduce power consumption and other factors. Currently, techniques like fuzzy logic and additional optimizations need higher logic than binary logic to enhance accuracy. The graphene nanoribbon field-effect transistor (GNRFET) seems to be very promising for building MVL logic and arithmetic circuits due to its remarkable electrical characteristics. This is because the GNRFET may adjust the threshold voltage by changing the GNR width. Carbon nano tube FET (CNTFET) has enormous potential in arithmetic and logic circuit that are mainly focused for 5G high speed processor with low power consumption [7].