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Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications | IEEE Conference Publication | IEEE Xplore

Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications


Abstract:

Power dissipation is one of the critical considerations while designing CMOS VLSI circuits for battery- and externally-powered embedded computer applications. This paper ...Show More

Abstract:

Power dissipation is one of the critical considerations while designing CMOS VLSI circuits for battery- and externally-powered embedded computer applications. This paper discusses a collection of methods that are well-suited for CMOS technology and are easily applicable to VLSI systems and circuit designers specifically for digital logic circuits, SRAM cells and Ternary Logic Gates. Supply-voltage-scaled CMOS is described as a low-power method for digital logic that provides a flexible design space for balancing energy (and power) consumption with circuit speed. Decoders are essential for VLSI and consideration for low power devices is in high demand as portability and battery become a challenge these days. In this paper, a review of techniques and circuits used for ternary logic gates is presented. Also, decoders using GNRFET and FinFET are simulated using HSPICE Tool. Scaling traditional complementary metal-oxide semiconductors (CMOS) has been plagued by issues such as the short channel effect and leakage power. Many transistors based on FinFET, GNRFETs, and DGFETs technologies are used to improve the performance metrics like power consumption, delay, IC area etc. Also, a comparative analysis shows a reduction in power of the order of 102 with 14T and 15T GNRFET based decoder over the MOSFET counterpart.
Date of Conference: 26-27 November 2022
Date Added to IEEE Xplore: 09 February 2023
ISBN Information:
Conference Location: Kolkata, India

I. Introduction

Low power design is required to reduce power consumption in high-end systems with high integration density. The low power method should be utilized throughout the design process, from system to process level, to optimize power dissipation [1]. Chips with high clock frequencies are being created due to increasing chip density and operation speed [2]. Even though the number of logic bits is the same, many valued logics may convey exponentially more data/information than binary logic [3] which is based on vertical channel FinFET with larger effective channel width, higher drive current capabilities in addition suppressed short channel effect at lower technology nodes (<22nm). Modern image and video processing systems, as well as DSP chips and microprocessors, need a high number of arithmetic operations [4]. Addition and subtraction are among the most fundamental mathematical operations, and they are extensively utilized in contemporary computer applications [5]. Soft errors in SRAMs are becoming more frequent as CMOS technology advances [6]. The requirement for transistor technology changes raises the chance of error [5]. Where data is absent, ternary logic gates are needed. As a result, multi-valued logic is presently being researched to reduce power consumption and other factors. Currently, techniques like fuzzy logic and additional optimizations need higher logic than binary logic to enhance accuracy. The graphene nanoribbon field-effect transistor (GNRFET) seems to be very promising for building MVL logic and arithmetic circuits due to its remarkable electrical characteristics. This is because the GNRFET may adjust the threshold voltage by changing the GNR width. Carbon nano tube FET (CNTFET) has enormous potential in arithmetic and logic circuit that are mainly focused for 5G high speed processor with low power consumption [7].

References

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