I. Introduction
The digital calculation is executed usually based on the 2-valued logic, having only two feasible values (1 or 0 and T or F) of the Boolean expression. The Multiple-valued logic (MVL) acts as an alternate to the conventional Boolean characterization of variables which may be using either infinitely or finitely various values like fuzzy logic [1] or ternary logic [2]. The Ternary logic, which is usually a three valued one, has gained a great attraction through its considerable advantages over the binary logic in designing the Very Large Scale Integrated Systems (VLSI) systems. Since, the Ternary logic minimizes the chip along with the complexity of the interconnects, it achieves energy efficiency and simplicity in designing the digital circuits [3]. Furthermore, the incorporation of Ternary logic makes the serial-parallel and serial arithmetic operations to perform faster. Progressive research has been done on ternary logic's implementation and design using a Complementary Metal oxide Semiconductor (CMOS) [4]. Usage of efficient MVL implementation for the 32-bits signed multiplier, about 50% of power dissipation and chip area can be reduced when compared to the binary logic [5]. In many cases, MVL and binary logics are combined for the enhancement in performance of CMOS technologies [6].