An Efficient Hardware Accelerator For Lossless Data Compression

Data compression is a trending field that is used in data storage and data transmission systems. Lossy compression means that data cannot be completely retrieved while in lossless compression the compressed data must be reconstructed exactly. Lossless data compression is used in compressing binary files, telemetry data and high-fidelity medical and scientific images where details are crucial. There is no generic compression algorithm that gives best compression ratio on all data pattern. In this paper, we propose a hybrid lossless hardware architecture that compresses most of data patterns such as repeated data, Gaussian distribution data and images. A profiling-before-compressing and then choosing the right compression hardware is proposed. The proposed design is a highly parallelized architecture that can compress/decompress 64 bytes/cycle with minor overhead. Moreover, it provides high compression ratio on small block sizes as well as large ones.

I. Introduction

Data compression is used to save storage space and bandwidth during data transmission. Most of data compression algorithms are often implemented in software. Software implementation allows later modifications or updates. Although software implementations are flexible, they are performance bottleneck. Software implementations are always focused on reaching the best compression ratios without taking execution speed into consideration. However, execution speed of compression as well as decompression is more important in some applications [10].