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Ravi Rajwar - IEEE Xplore Author Profile

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Author details

Ravi Rajwar

Also published under: R. Rajwar

Publications

16

Citations

965

Publications by Year

20002015

Co-Authors:

H. AkkaryAtiq A. BajwaBrent BoswellEdward BurtonTed Burton

Show All Co-Authors (55)

Ravi Rajwar

Also published under: R. Rajwar

Affiliation

Intel Corporation, Hillsboro, OR

Publication Topics

Critical Section,
Data Cache,
Serialized,
Abortion Rate,
Agent System,
Data Structure,
Educational Settings,
L2 Cache,
Memory Allocation,
Microarchitecture,
Synchronization,
Voltage Regulation

Biography

Ravi Rajwar (S'91–M'02) received the Ph.D. degree in computer science from the University of Wisconsin-Madison, Madison, WI, USA.,He joined Intel Corporation, Hillsboro, OR, USA, in 2002, where he is a Principal Engineer in the Product Development Architecture Group. He is currently working on various aspects of CPU and SoC architecture and development.(Based on document published on 25 November 2014).

Publications

16

Citations

965

Publications by Year

20002015

Co-Authors:

H. Akkary
Atiq A. Bajwa
Brent Boswell
Edward Burton
Ted Burton

Show All Co-Authors (55)

Author's Published Works

Search History

Showing 1-16 of 16 results

Conferences (9)

Magazines (6)

Journals (1)

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Single Year
R. Rajwar(10)
Ravi Rajwar(6)
H. Akkary(5)
S.T. Srinivasan(4)
A. Gandhi(3)
Intel(2)
Intel Microarchitecture Research Laboratory(2)
Computer Sciences Department, University of Wisconsin, Madison, Madison, WI, USA(2)
Microprocessor Research Laboratories, Intel Corporation, Hillsboro, OR, USA(2)
University of Illinois, Urbana-Champaign, USA(2)
IEEE Micro(6)
32nd International Symposium on Computer Architecture (ISCA'05)(2)
2007 IEEE 10th International Symposium on Workload Characterization(1)
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)(1)
IEEE Journal of Solid-State Circuits(1)
IEEE(16)
Madison, WI, USA(2)
Austin, TX, USA(1)
Boston, MA, USA(1)
Denver, CO, USA(1)
Monterrey, Mexico(1)
Data Cache(11)
Cache Misses(8)
Critical Section(7)
Serialized(7)
Benchmark(5)

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Haswell: A Family of IA 22 nm Processors

Nasser Kurd;Muntaquim Chowdhury;Edward Burton;Thomas P. Thomas;Christopher Mozak;Brent Boswell;Praveen Mosalikanti;Mark Neidengard;Anant Deval;Ashish Khanna;Nasirul Chowdhury;Ravi Rajwar;Timothy M. Wilson;Rajesh Kumar

IEEE Journal of Solid-State Circuits

Year: 2015 | Volume: 50, Issue: 1 | Journal Article |

Cited by: Papers (49)

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We describe the 4th Generation Intel® Core™ processor family (codenamed “Haswell”) implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include...Show More

Haswell: A Family of IA 22 nm Processors

Nasser Kurd;Muntaquim Chowdhury;Edward Burton;Thomas P. Thomas;Christopher Mozak;Brent Boswell;Praveen Mosalikanti;Mark Neidengard;Anant Deval;Ashish Khanna;Nasirul Chowdhury;Ravi Rajwar;Timothy M. Wilson;Rajesh Kumar

IEEE Journal of Solid-State Circuits

Year: 2015 | Volume: 50, Issue: 1 | Journal Article |

Improving in-memory database index performance with Intel® Transactional Synchronization Extensions

Tomas Karnagel;Roman Dementiev;Ravi Rajwar;Konrad Lai;Thomas Legler;Benjamin Schlegel;Wolfgang Lehner

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

Year: 2014 | Conference Paper |

Cited by: Papers (36)

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The increasing number of cores every generation poses challenges for high-performance in-memory database systems. While these systems use sophisticated high-level algorithms to partition a query or run multiple queries in parallel, they also utilize low-level synchronization mechanisms to synchronize access to internal database data structures. Developers often spend significant development and ve...Show More

Improving in-memory database index performance with Intel® Transactional Synchronization Extensions

Tomas Karnagel;Roman Dementiev;Ravi Rajwar;Konrad Lai;Thomas Legler;Benjamin Schlegel;Wolfgang Lehner

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)

Year: 2014 | Conference Paper |

Haswell: The Fourth-Generation Intel Core Processor

Per Hammarlund;Alberto J. Martinez;Atiq A. Bajwa;David L. Hill;Erik Hallnor;Hong Jiang;Martin Dixon;Michael Derr;Mikal Hunsaker;Rajesh Kumar;Randy B. Osborne;Ravi Rajwar;Ronak Singhal;Reynold D'Sa;Robert Chappell;Shiv Kaushik;Srinivas Chennupaty;Stephan Jourdan;Steve Gunther;Tom Piazza;Ted Burton

Year: 2014 | Volume: 34, Issue: 2 | Magazine Article |

Cited by: Papers (186) | Patents (1)

HTML

Haswell, Intel's fourth-generation core processor architecture, delivers a range of client parts, a converged core for the client and server, and technologies used across many products. It uses an optimized version of Intel 22-nm process technology. Haswell provides enhancements in power-performance efficiency, power management, form factor and cost, core and uncore microarchitecture, and the core...Show More

Haswell: The Fourth-Generation Intel Core Processor

Per Hammarlund;Alberto J. Martinez;Atiq A. Bajwa;David L. Hill;Erik Hallnor;Hong Jiang;Martin Dixon;Michael Derr;Mikal Hunsaker;Rajesh Kumar;Randy B. Osborne;Ravi Rajwar;Ronak Singhal;Reynold D'Sa;Robert Chappell;Shiv Kaushik;Srinivas Chennupaty;Stephan Jourdan;Steve Gunther;Tom Piazza;Ted Burton

Year: 2014 | Volume: 34, Issue: 2 | Magazine Article |

Performance evaluation of Intel® Transactional Synchronization Extensions for high-performance computing

Richard M. Yoo;Christopher J. Hughes;Konrad Lai;Ravi Rajwar

SC '13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

Year: 2013 | Conference Paper |

Cited by: Papers (56) | Patents (2)

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Intel has recently introduced Intel® Transactional Synchronization Extensions (Intel® TSX) in the Intel 4th Generation Core™ Processors. With Intel TSX, a processor can dynamically determine whether threads need to serialize through lock-protected critical sections. In this paper, we evaluate the first hardware implementation of Intel TSX using a set of high-performance computing (HPC) workloads, ...Show More

Performance evaluation of Intel® Transactional Synchronization Extensions for high-performance computing

Richard M. Yoo;Christopher J. Hughes;Konrad Lai;Ravi Rajwar

SC '13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

Year: 2013 | Conference Paper |

Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation

Naveen Neelakantam;Ravi Rajwar;Suresh Srinivas;Uma Srinivasan;Craig Zilles

Year: 2008 | Volume: 28, Issue: 1 | Magazine Article |

Cited by: Papers (3)

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Technology trends and shrinking power envelopes have forced microprocessor designers to focus on hardware techniques that efficiently improve single-thread performance without superlinear increases in power and silicon area. In this article, we identify hardware atomic execution - the execution of a region of code completely or not at all - as such a feature for simplifying existing and enabling n...Show More

Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation

Naveen Neelakantam;Ravi Rajwar;Suresh Srinivas;Uma Srinivasan;Craig Zilles

Year: 2008 | Volume: 28, Issue: 1 | Magazine Article |

Implications of False Conflict Rate Trends for Robust Software Transactional Memory

Craig Zilles;Ravi Rajwar

2007 IEEE 10th International Symposium on Workload Characterization

Year: 2007 | Conference Paper |

Cited by: Papers (6)

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We demonstrate that a common optimization for reducing the single-thread overhead of word-based Software Transactional Memory (STM) systems can have a significant negative impact on their scalability. Specifically, we find that the use of a tagless ownership table incurs false conflicts at a rate that grows superlinearly with both the TM data footprint and concurrency, and that increasing the size...Show More

Implications of False Conflict Rate Trends for Robust Software Transactional Memory

Craig Zilles;Ravi Rajwar

2007 IEEE 10th International Symposium on Workload Characterization

Year: 2007 | Conference Paper |

Scalable Load and Store Processing in Latency-Tolerant Processors

A. Gandhi;H. Akkary;R. Rajwar;S.T. Srinivasan;K. Lai

Year: 2006 | Volume: 26, Issue: 1 | Magazine Article |

Cited by: Papers (2)

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Memory latency tolerant architectures achieve high performance by supporting thousands of in-flight instructions without scaling cycle-critical processor resources. We present new load-store processing algorithms for latency tolerant architectures. We augment primary load and store queues with secondary buffers. The secondary load buffer is a set associative structure, similar to a cache. The seco...Show More

Scalable Load and Store Processing in Latency-Tolerant Processors

A. Gandhi;H. Akkary;R. Rajwar;S.T. Srinivasan;K. Lai

Year: 2006 | Volume: 26, Issue: 1 | Magazine Article |

Virtualizing transactional memory

R. Rajwar;M. Herlihy;K. Lai

32nd International Symposium on Computer Architecture (ISCA'05)

Year: 2005 | Conference Paper |

Cited by: Papers (182) | Patents (41)

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Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from well-known limitations, so researchers have considered nonblocking transactions as an alternative. Recent hardware proposals have demonstrated how transactions can achieve high performance while not suffering limitations of lock-based mechanism...Show More

Virtualizing transactional memory

R. Rajwar;M. Herlihy;K. Lai

32nd International Symposium on Computer Architecture (ISCA'05)

Year: 2005 | Conference Paper |

Scalable load and store processing in latency tolerant processors

A. Gandhi;H. Akkary;R. Rajwar;S.T. Srinivasasn;K. Lai

32nd International Symposium on Computer Architecture (ISCA'05)

Year: 2005 | Conference Paper |

Cited by: Papers (40) | Patents (8)

HTML

Memory latency tolerant architectures support thousands of in-flight instructions without scaling cycle-critical processor resources, and thousands of useful instructions can complete in parallel with a miss to memory. These architectures however require large queues to track all loads and stores executed while a miss is pending. Hierarchical designs alleviate cycle time impact of these structures...Show More

Scalable load and store processing in latency tolerant processors

A. Gandhi;H. Akkary;R. Rajwar;S.T. Srinivasasn;K. Lai

32nd International Symposium on Computer Architecture (ISCA'05)

Year: 2005 | Conference Paper |

Continual flow pipelines: achieving resource-efficient latency tolerance

S.T. Srinivasan;R. Rajwar;H. Akkary;A. Gandhi;M. Upton

Year: 2004 | Volume: 24, Issue: 6 | Magazine Article |

Cited by: Papers (24) | Patents (2)

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With the natural trend toward integration, microprocessors are increasingly supporting multiple cores on a single chip. To keep design effort and costs down, designers of these multicore microprocessors frequently target an entire product range, from mobile laptops to high-end servers. This article discusses a continual flow pipeline (CFP) processor. Such processor architecture can sustain a large...Show More

Continual flow pipelines: achieving resource-efficient latency tolerance

S.T. Srinivasan;R. Rajwar;H. Akkary;A. Gandhi;M. Upton

Year: 2004 | Volume: 24, Issue: 6 | Magazine Article |

Transactional execution: toward reliable, high-performance multithreading

R. Rajwar;J. Goodman

Year: 2003 | Volume: 23, Issue: 6 | Magazine Article |

Cited by: Papers (19) | Patents (30)

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Although lock-based critical sections are the synchronization method of choice, they have significant performance limitations and lack certain properties, such as failure atomicity and stability. Addressing both these limitations requires considerable software overhead. Transactional lock removal can dynamically eliminate synchronization operations and achieve transparent transactional execution b...Show More

Transactional execution: toward reliable, high-performance multithreading

R. Rajwar;J. Goodman

Year: 2003 | Volume: 23, Issue: 6 | Magazine Article |

Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers

H. Akkary;R. Rajwar;S.T. Srinivasan

Year: 2003 | Volume: 23, Issue: 6 | Magazine Article |

Cited by: Papers (9) | Patents (14)

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Processors require a combination of large instruction windows and high clock frequency to achieve high performance. Traditional processors use reorder buffers, but these structures do not scale efficiently as window size increases. A new technique, checkpoint processing and recovery, offers an efficient means of increasing the instruction window size without requiring large, cycle-critical structu...Show More

Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers

H. Akkary;R. Rajwar;S.T. Srinivasan

Year: 2003 | Volume: 23, Issue: 6 | Magazine Article |

Checkpoint processing and recovery: towards scalable large instruction window processors

H. Akkary;R. Rajwar;S.T. Srinivasan

Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.

Year: 2003 | Conference Paper |

Cited by: Papers (144) | Patents (46)

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Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically required to buffer and process such instruction window sizes significantly degrade the cycle time. This paper proposes a checkpoint processing and recovery (CPR) microarchitecture, and shows how to implement a large instruct...Show More

Checkpoint processing and recovery: towards scalable large instruction window processors

H. Akkary;R. Rajwar;S.T. Srinivasan

Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36.

Year: 2003 | Conference Paper |

An architectural evaluation of Java TPC-W

H.W. Cain;R. Rajwar;M. Marden;M.H. Lipasti

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture

Year: 2001 | Conference Paper |

Cited by: Papers (66) | Patents (4)

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The use of the Java programming language for implementing server-side application logic is increasingly in popularity yet there is very little known about the architectural requirements of this emerging commercial workload. We present a detailed characterization of the Transaction Processing Council's TPC-W web benchmark, implemented in Java. The TPC-W benchmark is designed to exercise the web ser...Show More

An architectural evaluation of Java TPC-W

H.W. Cain;R. Rajwar;M. Marden;M.H. Lipasti

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture

Year: 2001 | Conference Paper |

Speculative lock elision: enabling highly concurrent multithreaded execution

R. Rajwar;J.R. Goodman

Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34

Year: 2001 | Conference Paper |

Cited by: Papers (130) | Patents (116)

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Serialization of threads due to critical sections is a fundamental bottleneck to achieving high performance in multithreaded programs. Dynamically, such serialization may be unnecessary because these critical sections could have safely executed concurrently without locks. Current processors cannot fully exploit such parallelism because they do not have mechanisms to dynamically detect such false i...Show More

Speculative lock elision: enabling highly concurrent multithreaded execution

R. Rajwar;J.R. Goodman

Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34

Year: 2001 | Conference Paper |

Improving the throughput of synchronization by insertion of delays

R. Rajwar;A. Kagi;J.R. Goodman

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

Year: 2000 | Conference Paper |

Cited by: Papers (13) | Patents (33)

Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor and interprocessor communication may further compromise the scalability of these primitives. Ideally, synchronization primitives should provide high performance under both high and low contention without requiring substan...Show More

Improving the throughput of synchronization by insertion of delays

R. Rajwar;A. Kagi;J.R. Goodman

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

Year: 2000 | Conference Paper |

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