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Zongxuan Sun - IEEE Xplore Author Profile

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Due to the rise in the number of cores in modern multicore architectures, 3-D integration (i.e., vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a drastic reduction in global interconnect lengths and die footprint compared with 2-D counterparts. However, thermal issues are predominant in 3-D-SOCs due to the vertical stacking nature of chips which multiplies...Show More
The presence of multiple cores in modern multicore architectures makes thermal management and temperature estimation a really challenging task for enhancing reliability and lifespan. Due to the presence of many cores, the core/tile spacing needs to be optimized in order to enhance the thermal coupling between interconnect routing blocks and active tiles. In addition, the tiles activity patterns un...Show More
In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and M0 filling through S/D trenched regions in addition to the conventional scheme where metal (M0) epi on the S/D. The device ET performance is enhanced ...Show More
BiCMOS technology can be a possible replacement for FDSOI and FinFET technology due to their higher transconductance, which allows them to operate at in THz range i.e. radio frequencies (RF) in addition to their higher voltage handling ability. The most advanced SiGe heterojunction bipolar transistor (HBT) technology (55-nm BiCMOS) demonstrates room temperature cut-off frequency (f_{\mathrm{t}})...Show More
With scaling FinFETs in advanced logic technologies, fin thickness, source/drain (S/D) regions doping and lattice hot-spot temperature predominantly affect the fin channel thermal conductivity due to enhanced phonon boundary scattering and phonon-dopant impurity (mass and size) fluctuations and leads to more device SHE. In this paper, we investigated these effects on silicon-on-insulator (SOI) fin...Show More
This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron-phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simula...Show More
In this paper, work function variability (WFV) of stacked nanosheet FET (NSHFET) has been numerically investigated using 3-D quantum corrected Drift-Diffusion simulation framework for sub-7nm high performance logic applications. The WFV induced NSHFET performance is investigated using RGG (ratio of average grain size to gate area) plot for fair comparison against nanowire FET (NWFET) as the effect...Show More
We have studied the impact of thermal contact resistance (TCR) (Rth) and within-chip ambient temperature (TA) on the device self-heating effect (SHE) and its effect on transient and steady-state performance of Si 3Fin FinFET-based CMOS inverter (from N-14 to N-7 technologies) using coupled hydrodynamic-thermodynamic (HD-TH) mixed-mode simulations. The effect of the load capacitance (CL) on device ...Show More
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra dow...Show More
Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through t...Show More