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A. Viviani

Publications

Citations

368

Publications by Year

19952001

Co-Authors:

S. AdriaensenJ. -P. ColingeP. DelatteL. DemeusV. Dessard

Show All Co-Authors (12)

A. Viviani

Affiliation

Microelectronics Laboratory

Université Catholique de Louvain

Louvain-la-Neuve, Belgium

Publication Topics

Analog Circuits,
Supply Voltage,
Threshold Voltage,
Total Harmonic Distortion,
Bias Current,
Elevated Temperature,
High Temperature,
Impedance,
Large Temperature Range,
Temperature Range,
Thin-film Technology,
Aerospace Applications

Biography

Alberto Viviani received the “Laureat” degree in electrical engineering from the Universita degli Studi di Genova, Genoa, Italy, in 1994. He is currently working toward the Ph.D. degree at the Université Catholique de Louvain, Louvain-La-Neuve, Belgium.,He is currently with Sipex Corporation, Zaventem, Belgium. His research interests include analog design in thin-film SOI technology and implementation of ΣΔ modulators for low-power and high-temperature applications.(Based on document published on 7 August 2002).

Publications

Citations

368

Publications by Year

19952001

Co-Authors:

S. Adriaensen
J. -P. Colinge
P. Delatte
L. Demeus
V. Dessard

Show All Co-Authors (12)

Author's Published Works

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Showing 1-9 of 9 results

Conferences (6)

Journals (3)

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Single Year
A. Viviani(9)
D. Flandre(9)
L. Demeus(4)
B. Gentinne(3)
V. Dessard(3)
Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la-Neuve, Belgium(3)
Microelectronics Laboratories, Université Catholique de Louvain, Louvain-la-Neuve, Belgium(1)
Microelectronics, Université Catholique de Louvain, Louvain-la-Neuve, Belgium(1)
Alcatel Microelectronics, Oudenaarde, Belgium(1)
Laboratoire de Microélectronique, Université catholique de Louvain, Belgium(1)
1996 IEEE International SOI Conference Proceedings(1)
1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145)(1)
ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference(1)
HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)(1)
IEEE Journal of Solid-State Circuits(1)
IEEE(9)
Albuquerque, NM, USA(1)
Berlin, Germany(1)
Neuchatel, Switzerland(1)
Sanibel Island, FL, USA(1)
The Hague, Netherlands(1)
Threshold Voltage(4)
Analog Circuits(3)
Bias Current(3)
Poles And Zeros(3)
Supply Voltage(3)

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Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications

L. Demeus;V. Dessard;A. Viviani;S. Adriaensen;D. Flandre

IEEE Transactions on Industrial Electronics

Year: 2001 | Volume: 48, Issue: 2 | Journal Article |

Cited by: Papers (18)

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The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated...Show More

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications

L. Demeus;V. Dessard;A. Viviani;S. Adriaensen;D. Flandre

IEEE Transactions on Industrial Electronics

Year: 2001 | Volume: 48, Issue: 2 | Journal Article |

The art of high temperature FD-SOI CMOS

L. Demeus;P. Delatte;V. Dessard;S. Adriaensen;A. Viviani;C. Renaux;D. Flandre

HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)

Year: 1999 | Conference Paper |

Cited by: Papers (3)

This paper presents the latest results of our research on SOI (Silicon-On-Insulator) technology for high temperature electronics. We focus on Fully-Depleted SOI (FD-SOI) because it achieves superior high temperature results compared with Partially Depleted (PD-SOI) technology. Our interest includes both technology considerations and circuit studies. We show that FD-SOI is an efficient way to imple...Show More

The art of high temperature FD-SOI CMOS

L. Demeus;P. Delatte;V. Dessard;S. Adriaensen;A. Viviani;C. Renaux;D. Flandre

HITEN 99. Third European Conference on High Temperature Electronics. (IEEE Cat. No.99EX372)

Year: 1999 | Conference Paper |

Design and application of SOI CMOS OTAs for high-temperature environments

D. Flandre;L. Demeus;V. Dessard;A. Viviani;B. Gentinne;J.-P. Eggermont

Proceedings of the 24th European Solid-State Circuits Conference

Year: 1998 | Conference Paper |

Cited by: Papers (4)

Special techniques are presented for the design of SOI CMOS OTAs which have to operate from room up to very high ambient temperatures. The results of several implementations are reported including applications such as in bandgap and current references as well as Σ-Δ modulators with efficient switch design at elevated temperatures.Show More

Design and application of SOI CMOS OTAs for high-temperature environments

D. Flandre;L. Demeus;V. Dessard;A. Viviani;B. Gentinne;J.-P. Eggermont

Proceedings of the 24th European Solid-State Circuits Conference

Year: 1998 | Conference Paper |

High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology

L. Demeus;A. Viviani;D. Flandre

1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145)

Year: 1998 | Conference Paper |

Cited by: Papers (2) | Patents (1)

The feasibility of single chip solutions fully integrating complete analog instrumentation system using thin-film fully-depleted SOI CMOS technology is demonstrated. The performance of our instrumentation amplifiers, continuous-time filters and sigma-delta modulators are compatible with actual specifications from oil drilling or aerospace applications and correct operation is extended up to more t...Show More

High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology

L. Demeus;A. Viviani;D. Flandre

1998 Fourth International High Temperature Electronics Conference. HITEC (Cat. No.98EX145)

Year: 1998 | Conference Paper |

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

D. Flandre;A. Viviani;J.-P. Eggermont;B. Gentinne;P.G.A. Jespers

IEEE Journal of Solid-State Circuits

Year: 1997 | Volume: 32, Issue: 7 | Journal Article |

Cited by: Papers (73) | Patents (2)

A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the "gm/ID" methodology is considered further on for quick optimization of the architecture based on the dc o...Show More

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

D. Flandre;A. Viviani;J.-P. Eggermont;B. Gentinne;P.G.A. Jespers

IEEE Journal of Solid-State Circuits

Year: 1997 | Volume: 32, Issue: 7 | Journal Article |

Substrate crosstalk reduction using SOI technology

J.-P. Raskin;A. Viviani;D. Flandre;J.-P. Colinge

IEEE Transactions on Electron Devices

Year: 1997 | Volume: 44, Issue: 12 | Journal Article |

Cited by: Papers (238) | Patents (182)

This work analyzes both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compares them to those of normal bulk CMOS process. The influence of various parameters, such as substrate resistivity, buried oxide thickness and distance between devices, is investigated. The use of capacitive guard rings is proposed, and their effe...Show More

Substrate crosstalk reduction using SOI technology

J.-P. Raskin;A. Viviani;D. Flandre;J.-P. Colinge

IEEE Transactions on Electron Devices

Year: 1997 | Volume: 44, Issue: 12 | Journal Article |

Design Methodology for CMOS Gain-Boosted Folded-Cascode OTA with Application to SOI technology

D. Flandre;A. Viviani;J.-P. Eggermont;B. Gentinne;P. Jespers

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference

Year: 1996 | Conference Paper |

Cited by: Papers (6)

Equations, criteria and procedures are presented for the design of gain-boosted folded-cascode CMOS OTAs and applied to bulk and SOI implementations and comparisons.Show More

Design Methodology for CMOS Gain-Boosted Folded-Cascode OTA with Application to SOI technology

D. Flandre;A. Viviani;J.-P. Eggermont;B. Gentinne;P. Jespers

ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference

Year: 1996 | Conference Paper |

A SOI-CMOS micro-power first-order sigma-delta modulator

A. Viviani;D. Flandre;P. Jespers

1996 IEEE International SOI Conference Proceedings

Year: 1996 | Conference Paper |

Cited by: Papers (1)

The low-power and high-temperature potentials of SOI have been used to design a /spl Sigma//spl Delta/ modulator that achieves performances hard to obtain in bulk technology. From this first study, we estimate that further improvements based on the use of a technology with lower transistor size and lower threshold voltage, together with higher-order loop filters and higher OSR could boost the prec...Show More

A SOI-CMOS micro-power first-order sigma-delta modulator

A. Viviani;D. Flandre;P. Jespers

1996 IEEE International SOI Conference Proceedings

Year: 1996 | Conference Paper |

Extended study of crosstalk in SOI-SIMOX substrates

A. Viviani;J.P. Raskin;D. Flandre;J.P. Colinge;D. Vanhoenacker

Proceedings of International Electron Devices Meeting

Year: 1995 | Conference Paper |

Cited by: Papers (23) | Patents (8)

This work analyzes crosstalk phenomena in SOI-SIMOX substrates by means of two-dimensional device simulations and measurements on test structures. The influence of the substrate resistivity and of guard rings is studied. The results are compared with those obtained for standard CMOS technology. A significant crosstalk reduction, up to 10 GHz, is obtained with high-resistivity substrates. A simple ...

First Page of the Article

Extended study of crosstalk in SOI-SIMOX substrates

A. Viviani;J.P. Raskin;D. Flandre;J.P. Colinge;D. Vanhoenacker

Proceedings of International Electron Devices Meeting

Year: 1995 | Conference Paper |

Author details

A. Viviani

A. Viviani

Affiliation

Publication Topics

Biography

Showing 1-9 of 9 results

Show

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications

Integrated sensor and electronic circuits in fully depleted SOI technology for high-temperature applications

The art of high temperature FD-SOI CMOS

The art of high temperature FD-SOI CMOS

Design and application of SOI CMOS OTAs for high-temperature environments

Design and application of SOI CMOS OTAs for high-temperature environments

High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology

High-temperature analog instrumentation system in thin-film fully-depleted SOI CMOS technology

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Substrate crosstalk reduction using SOI technology

Substrate crosstalk reduction using SOI technology

Design Methodology for CMOS Gain-Boosted Folded-Cascode OTA with Application to SOI technology

Design Methodology for CMOS Gain-Boosted Folded-Cascode OTA with Application to SOI technology

A SOI-CMOS micro-power first-order sigma-delta modulator

A SOI-CMOS micro-power first-order sigma-delta modulator

Extended study of crosstalk in SOI-SIMOX substrates

Extended study of crosstalk in SOI-SIMOX substrates

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