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This paper describes two advanced technologies recently adopted in back-end-of-line (BEOL) process for our logic products: self-aligned-universal-patterning (SAUP) and sacrificial oxide layer (SOL). Advantages of SAUP include improved extreme ultraviolet (EUV) throughput, reduced pinch-off type patterning defects, improved reliability, and lower power rail resistance. SOL is found to be an effecti...Show More
We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Da...Show More
We demonstrate endurance characteristics of a 1T1C, 64 Mb FRAM in a real-time operational situation. To explore endurance properties in address access time tAA of 100 ns, we establish a measurement set-up that covers asymmetric pulse-chains corresponding to D1- and D0-READ/RESTORE/WRITE over a frequency range from 1.0 to 7.7 MHz. What has been achieved is that endurance cycles approximate 5.9 × 10...Show More
We discuss key technologies of 180 nm-node ferroelectric memories, whose process integration is becoming extremely complex when device dimension shrinks into a nano-scale. This is because process technology in ferroelectric integration does not extend to conventional shrink technology due to many difficulties of coping with MIM (Metal-Insulator-Metal) capacitors. The key integration technologies i...Show More
In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 μm2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key t...Show More
We have successfully demonstrated a world smallest 0.25 μm2 cell 1T1C 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The ne...Show More
64 Mb FRAM with ITIC (one-transistor and one-capacitor) cell architecture has progressed greatly for a robust level of reliability. Random-single-bits appeared from package-level tests are attributed mostly to extrinsic origins (e.g. interconnection failures) rather than intrinsic ones. The extrinsic failures can be linked to two activation energies: while one is 0.27 eV originated from oxygen-vac...Show More
64 Mb FRAM with a ITIC scheme has progressed greatly for mass production in terms of a highly reliable device. For the first time, package-level reliabilities of the memory were evaluated systematically and massively. We scrutinized the device reliabilities in accelerated manners, one of which is high-temperature-operating-life (HTOL) test; and the other is high-temperature-storage (HTS) test. Ran...Show More
We have successfully demonstrated a 0.34μm2 COB cell 1T1C 64Mb FRAM at 150nm technology node. The minimum signal window between data "1" and data "0" of 64M bit cells was evaluated to 300mV at 85°C, 1.6V VDD. This wide signal window was achieved by introducing advanced anneal technology and optimized capacitor layout, from which the variation of individual cell charge was greatly improved, along w...Show More