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Comprehensive Compact Phenomenological Modeling of Integrated Metal-Oxide Memristors
Hussein Nili;Adrien F. Vincent;Mirko Prezesio;Mohammad R. Mahmoodi;Irina Kataeva;Dmitri B. Strukov
We present a comprehensive phenomenological model for the crossbar integrated metal-oxide continuous-state memristors. The model consists of static and dynamic equations, which are obtained by fitting a large amount of experimental data, collected on several hundred devices. Model describes the average devices' I-V characteristics as well as their spatial (device-to-device) and temporal variations...Show More
Towards the Development of Analog Neuromorphic Chip Prototype with 2.4M Integrated Memristors
Irina Kataeva;Shigeki Ohtsuka;Hussein Nili;Hyungjin Kim;Yoshihiko Isobe;Koichi Yako;Dmitri Strukov
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2019 | Conference Paper |
Cited by: Papers (14)
We have designed and fabricated a neuromorphic accelerator chip which features 180-nm CMOS circuitry and 2.4-million 0.04-μm2-footprint Al2O3/TiO2-x memristors. Memristors were passively integrated on top of the CMOS wafer into 48×48 crossbar circuits, with a total of 1032 crossbars on a chip. Each memristive crossbar is accessed via on-chip CMOS interface circuits which are controlled by a custom...Show More
Memristor-based perceptron classifier: Increasing complexity and coping with imperfect hardware
Farnood Merrikh Bayat;Mirko Prezioso;Bhaswar Chakrabarti;Irina Kataeva;Dmitri Strukov
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Year: 2017 | Conference Paper |
Cited by: Papers (22)
We experimentally demonstrate classification of 4×4 binary images into 4 classes, using a 3-layer mixed-signal neuromorphic network (“MLP perceptron”), based on two passive 20×20 memristive crossbar arrays, board-integrated with discrete CMOS components. The network features 10 hidden-layer and 4 output-layer analog CMOS neurons and 428 metal-oxide memristors, i.e. is almost an order of magnitude ...Show More
Density-Based Data Pruning Method for Deep Reinforcement Learning
2016 15th IEEE International Conference on Machine Learning and Applications (ICMLA)
Year: 2016 | Conference Paper |
Cited by: Papers (3)
We present a density-based Data Pruning method for Deep Reinforcement Learning (DRL) to improve learning stability and long-term memory in rare situations. The method controls density distribution in the experience pool by discarding high correlation data and preserving rare and unique data. We apply our method to Deep Q-networks (DQN) and Deep Deterministic Policy Gradients (DDPG) for testing in ...Show More
Modeling and implementation of firing-rate neuromorphic-network classifiers with bilayer Pt/Al2O3/TiO2−x/Pt Memristors
M. Prezioso;I. Kataeva;F. Merrikh-Bayat;B. Hoskins;G. Adam;T. Sota;K. Likharev;D. Strukov
2015 IEEE International Electron Devices Meeting (IEDM)
Year: 2015 | Conference Paper |
Cited by: Papers (37)
Neuromorphic pattern classifiers were implemented, for the first time, using transistor-free integrated crossbar circuits with bilayer metal-oxide memristors. 10×6- and 10×8-crosspoint neuromorphic networks were trained in-situ using a Manhattan-Rule algorithm to separate a set of 3×3 binary images: into 3 classes using the batch-mode training, and into 4 classes using the stochastic-mode training...Show More
Efficient training algorithms for neural networks based on memristive crossbar circuits
Irina Kataeva;Farnood Merrikh-Bayat;Elham Zamanidoost;Dmitri Strukov
2015 International Joint Conference on Neural Networks (IJCNN)
Year: 2015 | Conference Paper |
We have adapted backpropagation algorithm for training multilayer perceptron classifier implemented with memristive crossbar circuits. The proposed training approach takes into account switching dynamics of a particular, though very typical, type of memristive devices and weight update restrictions imposed by crossbar topology. The simulation results show that for crossbar-based multilayer percept...Show More
Low area overhead in-situ training approach for memristor-based classifier
Elham Zamanidoost;Michael Klachko;Dmitri Strukov;Irina Kataeva
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)
Year: 2015 | Conference Paper |
Cited by: Papers (10)
We propose combination of "dropout" and "Manhattan Rule" training algorithms for memristive crossbar neural networks to reduce circuit area overhead of in-situ training. Using accurate phenomenological model of memristive devices, we show that such combination allows achieving 0.7% misclassification rate on the MNIST benchmark, which is comparable to the best reported results. At the same time, th...Show More
Manhattan rule training for memristive crossbar circuit pattern classifiers
Elham Zamanidoost;Farnood M. Bayat;Dmitri Strukov;Irina Kataeva
2015 IEEE 9th International Symposium on Intelligent Signal Processing (WISP) Proceedings
Year: 2015 | Conference Paper |
We investigated batch and stochastic Manhattan Rule algorithms for training multilayer perceptron classifiers implemented with memristive crossbar circuits. In Manhattan Rule training, the weights are updated only using sign information of classical backpropagation algorithm. The main advantage of Manhattan Rule is its simplicity, which leads to more compact hardware implementation and faster trai...Show More
Clock Line Considerations for an SFQ Large Scale Reconfigurable Data Paths Processor
Irina Kataeva;Hiroyuki Akaike;Akira Fujimaki;Nobuyuki Yoshikawa;Shuichi Nagasawa;Naofumi Takagi
We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between ...Show More
Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits
Farhad Mehdipour;Hiroaki Honda;Hiroshi Kataoka;Koji Inoue;Irina Kataeva;Kazuaki Murakami;Hiroyuki Akaike;Akira Fujimaki
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
Year: 2010 | Conference Paper |
Cited by: Papers (2)
To overcome issues originating from the CMOS technology, a large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits is introduced. LSRDP is augmented to a general purpose processor to accelerate the execution of data flow graphs (DFGs) extracted from scientific applications. Procedure of mapping large DFGs onto the LSRDP is discussed and our proposed techniques ...Show More
An Operand Routing Network for an SFQ Reconfigurable Data-Paths Processor
Irina Kataeva;Hiroyuki Akaike;Akira Fujimaki;Nobuyuki Yoshikawa;Naofumi Takagi;Koji Inoue;Hiroaki Honda;Kazuaki Murakami
We report the progress in the development of an operand routing network (ORN) for an SFQ reconfigurable data-paths processor (SFQ-RDP). The SFQ-RDP is implemented as a two-dimensional array of floating-point units (FPU), outputs of which can be connected to the inputs of one or more FPUs in the next row via ORN. We have considered two architectures of the ORN: one is based on NDRO switches and the...Show More
SFQ Propagation Properties in Passive Transmission Lines Based on a 10-Nb-Layer Structure
Katsumi Takagi;Masamitsu Tanaka;Shingo Iwasaki;Ryo Kasagi;Irina Kataeva;Shuichi Nagasawa;Tetsuro Satoh;Hiroyuki Akaike;Akira Fujimaki
We have studied single-flux-quantum (SFQ) propagation properties in passive transmission lines (PTLs) based on a 10-Nb-layer device structure (ADP2). In ADP2, we can use the PTLs with a line width about 5 mum, one seventh of conventional line width by adopting a strip line (SL) structure and increasing the characteristic impedance. The evaluation has been conducted on the PTL length and the via-ho...Show More
Scalable Matrix Multiplication With Hybrid CMOS-RSFQ Digital Signal Processor
We report an RSFQ digital signal processor design based on hybrid RSFQ-CMOS memory suitable for a general matrix-on-matrix multiplication algorithm. The DSP consists of an RSFQ multiply-accumulate unit, memory caches and synchronization block, partitioned into multiple chips, and a large CMOS memory. The parameters of the RSFQ DSP are a 10times10 bits multiplication with rounding to 14 bits, an 18...Show More
Room Temperature Interface for RSFQ Digital Signal Processor
Henrik Engseth;Raihan Rafique;Irina Kataeva;Samuel Intiso;Anna Kidiyarova-Shevchenko
This paper describes a cryogenic multi-chip module (MCM) probe for testing of a superconducting hybrid digital signal processor (DSP) capable of 24 giga multiply accumulate operations per second. The probe has 39 data channels with 4 GHz bandwidth, a 30 GHz high speed clock input line, and 48 biasing lines. The MCM interface board features 164 spring finger contacts for a 30 times 30 mm2 MCM. The ...Show More
RSFQ digital signal processor for interference cancellation
I. Kataeva;Hongxia Zhao;Henrik Engseth;E. Tolkacheva;A. Kidiyarova-Shevchenko
RSFQ high performance digital signal processor capable to perform up to 13 13-bit fixed-point GMACS has been designed for use in successive interference canceller in W-CDMA wireless systems. The performance of the processor has been verified by numerical simulations and VHDL simulation using accurate modeling of the RSFQ gates. Components of the processor, 4 /spl times/ 4 and 5 /spl times/ 5 paral...Show More
Time-delay optimization of RSFQ cells
S. Intiso;I. Kataeva;E. Tolkacheva;Henrik Engseth;K. Platov;A. Kidiyarova-Shevchenko
This paper presents timing models for RSFQ cells, based on conventional finite-state machines description. Models have been integrated, validated and verified in physical simulations and are suitable for VHDL design. A complete design flow from physical simulation to VHDL simulation, delays optimization, layouting and back-annotation is presented. The correctness of the timing models has been veri...Show More
Influence of the bias supply lines on the performance of RSFQ circuits
E. Tolkacheva;Henrik Engseth;I. Kataeva;A. Kidiyarova-Shevchenko
Two effects of the bias supply line on the performance of RSFQ circuits have been studied: inductive coupling between the bias supply line and circuit inductances; effect of the mirrored current in the ground plane. The following results of the study are presented: 3D calculations and experimental measurements of inductive coupling between parallel and perpendicular microstrips in presence of one ...Show More
RSFQ asynchronous serial multiplier and spreading codes generator for multiuser detector
A.Yu. Kidiyarova-Shevchenko;K.Yu. Platov;E.M. Tolkacheva;I.A. Kataeva
Serial multiplier and serial spreading code generators are vital elements of the RSFQ multiuser detector. We have designed different versions of both circuits to achieve maximum speed and at the same time minimize Josephson junction count. Comparison of different serial multipliers architectures supporting signed multiplication favored for asynchronous shifting over zero circuits based on carry sa...Show More
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