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A Digital Readout Integrated Circuit Based on Pixel-Level ADC Incorporating On-Chip Image Algorithm Calibration for IRFPA
Yan Zeng;Shiheng Yang;Yueduo Liu;Rongxin Bao;Zihao Zhu;Jiahui Lin;Xiong Zhou;Yong Chen;Jun Yin;Pui-In Mak;Qiang Li
This article presents a digital readout integrated circuit (DROIC) with fully ON-chip image algorithm calibration based on the pixel-level 18-bit analog-to-digital converter (ADC) for infrared focal plane array (IRFPA) applications. Such ON-chip calibrations include bad pixel compensation, nonuniformity correction, and background subtraction, which are implemented to avoid ON-chip memory storage f...Show More
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up
Zehao Zhang;Shiheng Yang;Yueduo Liu;Zihao Zhu;Jiahui Lin;Rongxin Bao;Tailong Xu;Zhizhan Yang;Mingkang Zhang;Jiaxin Liu;Xiong Zhou;Jun Yin;Pui-In Mak;Qiang Li
This brief presents an analytical treatment of the initial motional current ${i}_{m}{(}{0}{)}$ of the Pierce crystal oscillator (XO), which is critical for determining its start-up time ${T}_{s}$ . Specifically, the limitation of energy injection to boost ${i}_{m}{(}{0}{)}$ is studied, and the dc-settling process (DCS) at the dawn of the start-up for stimulating ${i}_{m}{(}{0}{)}$ is shown....Show More
A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS
Mingkang Zhang;Zihao Zhu;Yueduo Liu;Zehao Zhang;Rongxin Bao;Jiahui Lin;Haovu Zhuang;Jiaxin Liu;Xiong Zhou;Shiheng Yang;Qiang Li
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
Year: 2022 | Conference Paper |
This paper presents a low power, low phase noise, and small chip area transformer-based PMOS-only stacked-g», LC VCO in a 28-nm process. Both the top and bottom use PMOS cross-coupled pairs to provide negative resistances with suppressing the flicker noise. An interleaved transformer is used to get a higher coupling coefficient to achieve small chip area and high passive voltage gain. The VCO exhi...Show More
A 13-bit 1-MS/s SAR ADC With Rotation-Based Mismatch Error Cancellation
2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
This paper presents a mismatch error cancellation technique for high-resolution successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique that combines residue voltage oversampling and capacitors rotation significantly diminishes the impact of capacitor mismatch without calibration. A VCO-based comparator is adopted to achieve good noise performance with hig...Show More
A 100dB-TCMRR 8-Channel Bio-Potential Front-End with Multi-Channel Common-Mode Replication
2022 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2022 | Conference Paper |
For a multichannel bio-potential signal acquisition front-end, it's total CMRR (TCMRR) is restricted by these three factors: the inherent CMRR (ICMRR) of the amplifier used in the acquisition front-end, the impedance mismatch of electrodes, and the systematic mismatch due to the shared reference electrode. This paper presents a 8-channel bio-potential front-end with multi-channel common-mode repli...Show More
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop
Yueduo Liu;Rongxin Bao;Zihao Zhu;Shiheng Yang;Xiong Zhou;Jun Yin;Pui-In Mak;Qiang Li
An accurate performance evaluation of jitter-power figure-of-merit (FOM) for multiplying delay-locked loop (MDLL) is presented. For a typical MDLL employing a single-ended multiplying-delay ring voltage-controlled oscillator (MDVCO), it can be tuned via the capacitive loads to uphold a constant normalized phase noise (PN) across different frequencies for better jitter-power performance. Linear app...Show More
An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization
Pengfei Zhai;Zheng Zhu;Xiong Zhou;Yan Cai;Fan Zhang;Qiang Li
This article discusses the on-chip measurement of the power-supply noise (PSN) and demonstrates a scalable PSN spectrum analyzer with significantly improved speed and accuracy. Compressed sensing is exploited in the autocovariance-based measurement since the cyclostationary PSN is sparse. A six-level voltage-controlled oscillator (VCO)-based phase quantizer is proposed to improve the noise perform...Show More
A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication
High common-mode rejection ratio (CMRR) of an analog front end (AFE) requires high intrinsic CMRR of the front-end amplifier with high input common-mode (CM) impedance. This article presents a common-mode replication (CM-REP) technique, which replicates the input CM voltage over the front-end amplifier. By eliminating the CM current flow and its mismatch effect, CM-REP improves CMRR and input CM i...Show More
A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC
Xiaodan Zhou;Zehao Li;Yujie Wang;Xiong Zhou;Shiheng Yang;Jiaxin Liu;Qiang Li
2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
A low power and high-speed sample-and-hold (S/H) circuit which is suitable for the 16bit pipelined analog-to-digital converter (ADC) is proposed. By using the dynamic bias technique, The OTA in the S/H is realized with lower power dissipation. This S/H is fabricated in $0.18\ \mu\ \mathrm{m}$ mixed signal CMOS process and occupies 0.128mm2. It is integrated in a 16bit 25MS/s pipelined ADC which de...Show More
A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs
Bojun Hu;Sanfeng Zhang;Xiong Zhou;Zehao Li;Xiangxin Pan;Zhaoming Ding;Qiang Li
2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Year: 2021 | Conference Paper |
This paper presents a comparator speed enhancement technique for successive approximation register (SAR) analog-to-digital converter (ADC) under near- and sub-threshold supply voltages. The proposed delayed cross-coupling comparator effectively improves the speed of the comparator while maintaining a good noise performance. This work has been proved by a 350mV 8bit 12MS/s SAR ADC designed in a 65n...Show More
A Low-Power RC Oscillator with Offset and Path Delay Cancellation
Yueduo Liu;Zihao Zhu;Rongxin Bao;Shiheng Yang;Jiaxin Liu;Xiong Zhou;Qiang Li
2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
Year: 2021 | Conference Paper |
Cited by: Papers (4)
A 128-kHz RC time-constant-based relaxation oscillator is designed in 180-nm CMOS for ultra-low-power applications. The chopping structure and replica path delay loop are employed in this work to eliminate the effect of comparator offset and path delay respectively, leading to a frequency accuracy of ±0.21% over the temperature range from -20°C to 100 °C. The power consumption is 344 nW with 0.8-V...Show More
A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration
Yan Zeng;Shiheng Yang;Yueduo Liu;Zehao Li;Wengang Huang;Xiaozong Huang;Xiong Zhou;Jiaxin Liu;Qiang Li
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
Infrared focal plane arrays (IRFPAs) have been widely used in industrial, scientifical and medical imaging applications [1]–[5]. Due to the limitation of the manufacturing process, material quality and other factors, IRFPAs inevitably suffer from the current non-uniformity under the same light intensity; and the bad pixel with extreme photoelectric response which significantly degrade the quality ...Show More
A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS
Qiang Yu;Xiong Zhou;Kefeng Hu;Zijian Huang;Haiwen Chen;Xin Si;Jinda Yang;Qiang Li
ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
Year: 2021 | Conference Paper |
Cited by: Papers (4)
In this work, a 10b 400MS/s single-channel SAR ADC is reported. Without an auxiliary sub-ADC, a subranging architecture is proposed, where only one comparator is used with the subsetted capacitive DAC (CDAC), eliminating the mismatch of comparators and saving area. For the subranging process, a partial detect-and-skip (PDAS) switching scheme is proposed, which improves both power efficiency and li...Show More
A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs
Bojun Hu;Sanfeng Zhang;Xiong Zhou;Xiangxin Pan;Zhaoming Ding;Qiang Li
2021 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
This paper presents a sampling speed-enhancement technique for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove this technique. The post-layout simulat...Show More
Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs
Bojun Hu;Sanfeng Zhang;Xiangxin Pan;Xiangyu Zhao;Zhaoming Ding;Xiong Zhou;Shiheng Yang;Qiang Li
This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. Delayed cross-coupling comparator is introduced in this work, which enhances the comparator re...Show More
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming
High common-mode rejection ratio (CMRR) with concurrent electrode offset rejection is essential for physiological signal acquisitions. This article presents a CMRR enhancement technique for ac-coupled instrumentation amplifiers (ACIAs), where the mismatch of passive components limits the CMRR performance primarily. A modified chopping structure is proposed to mitigate the mismatch effect of the ps...Show More
25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing
Pengfei Zhai;Xiong Zhou;Yan Cai;Zheng Zhu;Fan Zhang;Qiang Li
2020 IEEE International Solid-State Circuits Conference - (ISSCC)
Year: 2020 | Conference Paper |
Cited by: Papers (1)
This work presents a fully integrated PSN analyzer with significantly improved measurement speed and noise performance. Compressed sensing is exploited due to the sparse nature of PSN signals. A VCO-based muiti-level phase quantizer is proposed, offering improved noise performance. A polyphase clock generator is also implemented on chip, enabling the whole system to work with only one external clo...Show More
23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication
2020 IEEE International Solid-State Circuits Conference - (ISSCC)
Year: 2020 | Conference Paper |
Cited by: Papers (11)
Interfacing with high-impedance sensors, such as dry-contacted electrodes and accelerometers requires high CMRR with sufficient input impedance concurrently. From the system point of view, the total CMRR (TCMRR) is determined by the intrinsic CMRR (ICMRR) of the front-end amplifier as well as the imbalance of source impedance; the latter has to be accommodated by large input common-mode (CM) imped...Show More
A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration
This article presents a 14-bit 4-MS/s voltage-controlled oscillator (VCO)-based successive approximation register (SAR) analog-to-digital converter (ADC), where the metastability of the VCO-based comparator is exploited for the background calibration of mismatch errors. A closed-form behavioral analysis of VCO-based comparators has been studied in the presence of noise, showing that the metastabil...Show More
A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV)2/sqrt(MHz) Noise Floor
Pengfei Zhai;Xiong Zhou;Yan Cai;Zheng Zhu;Fan Zhang;Zixiao Lin;Qiang Li
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2019 | Conference Paper |
Cited by: Papers (2)
This paper presents a multi-slice VCO-based quantizer (MSVQ) for high-resolution power supply noise analysis. To relax the trade-off between accuracy and measurement time, a multi-slice quantizer at a relatively higher sampling rate is proposed, and the auto-covariance replaces the autocorrelation to obtain PSD while immunes the spurs introduced by the quantizers itself and further reduces noise f...Show More
A 99.2 dB SNDR Feedforward Delta-Sigma Modulator with Build-In Summation Quantizer
2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)
Year: 2019 | Conference Paper |
A new type of quantizer with build-in weighted summation function is proposed for replacing summer in feedforward delta sigma modulators. To verify the validity, a 2nd-order 8-level modulator based on this quantizer has been implemented in 180 nm CMOS technology. Simulation results show that the modulator achieves a 99.2 dB SNDR in 25 kHz bandwidth while consumes 1.56 mW under 1.8 V supply.Show More
A Loss-Compensated 5-Bit Ka-Band Digital Phase Shifter with Low RMS Phase/Gain Error Over Wide Temperature Ranges
Ruoman Yang;Chao Liu;Xiangyu Zhao;Sheng Chang;Xiong Zhou;Qiang Li
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2019 | Conference Paper |
Cited by: Papers (3)
This paper presents the design and demonstration of a 5-bit Ka-band phase shifter with amplifiers to compensate for the passive loss using a 0.13-μm SiGe BiCMOS technology. Adopting the switched low-pass (LP)/high-pass (HP) networks in the phase shift stages, the phase shifter exhibits measured RMS phase and gain errors less than 4° and 0.6 dB, respectively, within the frequency range of 30-40 GHz...Show More
A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
Year: 2019 | Conference Paper |
Cited by: Papers (2)
This paper presents a 12-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 40nm CMOS technology. A VCO-based comparator is employed to adjust the noise level adaptively and its oscillation number is harnessed to bypass unnecessary cycles for saving energy. A 1-bit split-and-recombination redundancy and a digital error correction for bypass lo...Show More
Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators
Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-...Show More
A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator
A successive approximation register (SAR) analog-to-digital converter (ADC) with a voltage-controlled oscillator (VCO)-based comparator is presented in this paper. The relationship between the input voltage and the number of oscillation cycles (NOC) to reach a VCO-comparator decision is explored, implying an inherent coarse quantization in parallel with the normal comparison. The NOC as a design p...Show More
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