A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs

This paper presents a sampling speed-enhancement technique for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove this technique. The post-layout simulated SAR ADC consumes only 6.71/iW and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fj/convertion-step. Simulation results show the proposed speed-enhancement technique improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.

I. Introduction

With the intelligentization of medical instruments and the popularization of wearable devices, the interaction between digital and analog signals becomes more and more frequent. The miniaturization and portability of digital-analog hybrid devices puts forward higher requirements. Attributing the scaling down of feature sizes in advanced CMOS technologies, the standard supply voltages are getting lower. In order to achieve high speed under low voltages, pipeline [1] and flash [2] analog-to-digital converters (ADC) are designed to achieve tens of MHz sampling rate under 0.5V. But their figure-of-merits (FoMs) are not competitive as compared to successive approximation register (SAR) based ADCs due to the simple architecture with no need for power hungry modules. However, the working principle of SAR ADCs normally limits the sampling rate at hundreds of kS/s with supply voltages lower than 0.5V. This makes SAR ADC working at a higher sampling rate under low voltage conditions a hot research topic.