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Julien Dubois - IEEE Xplore Author Profile

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We propose a SVM-based approach to detect falls in several home environments using an optimised descriptor adapted to real-time tasks.We build an optimised spatio-temporal descriptor named STHFa_SBFS using several combinations of transformations of geometrical features, thanks to feature selection. We study the combinations of usual transformations of the features (Fourier Transform, Wavelet trans...Show More
We propose an automatic approach to detect falls in home environment. A Support Vector Machine based classifier is fed by a set of selected features extracted from human body silhouette tracking. The classifier is followed by filtering operations taking into account the temporal nature of a video. The features are based on height and width of human body bounding box, the user's trajectory with her...Show More
Motion estimation represents a key module in video compression. The Reconfigurable Video Coding context (RVC) requires proposing a flexible solution for motion estimation. The motion estimation performance should be modified to fit with the user or the environment's constraints. Depending on the required performances fixed by the application, a full search is sometimes not suitable, hence, alterna...Show More
Motion estimation represents a key module in video compression. The RVC context requires proposing a flexible solution for motion estimation. According to the nature of the application, a full search is sometimes not suitable, hence, alternative fast/reduced solutions should be considered. This paper proposes a model and implementation of a flexible motion estimation engine, which can be configure...Show More
The burrows-wheeler transform (BWT) is a combinatorial algorithm originally created for text compression such as bzip2, and that has been recently applied to image compression field. This paper focuses on the impact of compression scheme based on the combinatorial transform on high-level resolution medical images. It overviews the original scheme and some improvements that have been develop in pos...Show More
The face detection is a fundamental prerequisite step in the process of face recognition. The focus of this paper is the implementation of a real time embedded face detection system while relying on high level description language such as SystemC. Recently, the boosting based object detection algorithms proposed by have gained a lot of attention and are considered as the fastest accurate object de...Show More
The efficient implementation of multimedia algorithms, for the ever increasing complexity of the specifications and the emergence of the new generation of processing platforms characterized by multicore and multicomponent parallel architectures, requires appropriate design space exploration procedures as preliminary step for any implementation. This paper describes a new platform aiming at support...Show More
This paper describes a study for a real time embedded face detection system. Recently, the boosting based face detection algorithms proposed by [(Viola, P and Jone, M, 2001); (Lienhart, R, et al., 2003)] have gained a lot of attention and are considered as the fastest accurate face detection algorithms today. However, the embedded implementation of such algorithms into hardware is still a challeng...Show More
This paper describes a motion estimation co-processor architecture that explicitly separates the implementation stages consisting of data access to the search window and the evaluation of the matching criterion from the implementation of the search strategy. The architecture is modular and can be re-configured according to the different MPEG video coding profiles and level parameters. Although the...Show More
We propose a method of automatic hardware implementation of a decision rule based on the Adaboost algorithm. We review the principles of the classification method and we evaluate its hardware implementation cost in term of FPGA's slice, using different weak classifiers based on the general concept of hyperrectangle. We show how to combine the weak classifiers in order to find an efficient trade-of...Show More
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the full potential of CMOS selective access imaging technology. The processing features of the co-processor are functional to the specific acquisition process of CMOS sensors (random region acquisition, variable image size, vari...Show More