Loading [MathJax]/extensions/MathZoom.js
Guang Chen - IEEE Xplore Author Profile

Showing 1-13 of 13 results

Results

This paper reports new fully-CMOS-compatible on-chip RF inductors with Ni-Zn-Cu and Co2Z-type ferrite-partially-filled structures fabricated using a novel low-temperature nano-powder- mixed-photoresist filling technique. Measured improvements are up to +35% in L and +250% in Q across multi-GHz with f0 to 11.4 GHz.Show More
This paper reports fabrication and characterization of on-chip RF inductors with integrated Ni-Zn ferrite films using a novel powder-mixed-photoresist coating technique. Well crystallized Ni0.3Zn0.6Cu0.1Fe2O4 powders are mixed into photoresist and then coated on top of RF inductor spirals for performance improvement. This new low-temperature fabrication method is developed to eliminate any damage ...Show More
This letter reports the design and fabrication of on-chip radio-frequency (RF) inductors with integrated-ferrite thin films, which show substantial improvement over air-cored inductors, e.g., 19%–38% and 17%–28% increase in inductance $(L)$ for $\hbox{Y}_{2.8}\hbox{Bi}_{0.2}\hbox{Fe}_{5}\hbox{O}_{12}$ and $\hbox{Co}_{7}\hbox{ZrO}_{9}$ thin-film inductors, respectively, and 32%–55% improvement in q...Show More
This paper reports fabrication of on-chip RF integrated inductors with spin-coated ferrite thin-films (Ni-Zn-Cu-Fe-O, Y-Bi-Fe-O and Co-Zr-O) and high-frequency characterization using equivalent circuit model. Measurement results show that, compared with air-cored inductor, the inductance (L) of Y-Bi-Fe-O and Co-Zr-O thin-film samples increases by 26-50% and 20-39% in 0.1-9GHz, respectively; while ...Show More
Electrostatic discharge (ESD) is a serious IC reliability problem. On-chip ESD protection is used to protect ICs against ESD damage. This paper presents a real 3D mixed-mode ESD protection circuit simulation-design methodology for ESD design prediction. Practical ESD protection design examples in 0.35 /spl mu/m BiCMOS are given.Show More
On-chip ESD (electrostatic discharging) protection is a challenging IC design problem New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent ...Show More
This paper reviews the key issues in designing on-chip ESD (electrostatic discharge) protection structures for RF and microwave ICs. ESD protection basics, uniqueness in RF ESD protection, design methods, RF ESD protection characterization techniques and design optimization are discussed.Show More
The trial-and-error approach still dominates on-chip electrostatic discharge (ESD) protection circuit design. We present a new predictive mixed-mode ESD protection simulation-design methodology, which involves multiple-level electro-thermal-process-device-circuit-layout coupling in an ESD protection simulation that solves complex electro-thermal equations self-consistently at process, device and c...Show More
Several bonding-pad-oriented ESD protection structures, including a ggCMOS, an LVSCR and an all-direction ESD structures are reported, implemented in commercial 0.35 /spl mu/m CMOS and 0.6 /spl mu/m BiCMOS. Measurements agree with simulations well. HBM ESD zapping tests passed 2 kV, 4.4 kV and 14 kV, respectively. The structures are suitable ESD protection solutions for RF, mixed-signal and high-p...Show More
The challenges for developing an ESD (electrostatic discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction and device count reduction. This paper reports a new technology-independent layout extractor, ESDExtractor, which is capable of extracting all types of ESD devices and answers the demands for ESD design verification...Show More
Several techniques exist to realize low triggering of SCR (Si-controlled rectifier) ESD (electrostatic discharging) protection structures in CMOS technologies. This paper reports a novel RC-SCR (RC-coupled SCR) ESD protection circuit using a new RC-coupling-based triggering mechanism to further reduce triggering voltage. Implementation in a commercial 0.35/spl mu/m CMOS process results in a very l...Show More
An efficient device recognition algorithm is critical to ESD (electrostatic discharge) protection device extraction. In this paper, we propose a new algorithm based on a subgraph isomorphism, where subgraphs appearing multiple times within the same or different device model graphs are presented once only, thus reducing computational effort of detecting them in an input layout file. The mechanism t...Show More
The challenge in RF ESD protection circuit design, still a problem in definition, is to address the complex interactions between the ESD protection network and the circuit being protected in both directions. This paper discusses related key factors, e.g., switching and accidental triggering of ESD protection networks, as well as ESD-induced parasitic capacitive, resistive, noise coupling and self-...Show More