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Advanced 2.5D and 3D packaging technologies for next generation Silicon Photonics in high performance networking applications
Sandeep Razdan;Peter De Dobbelaere;Jie Xue;Aparna Prasad;Vipul Patel
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
Year: 2022 | Conference Paper |
Cited by: Papers (11)
We will discuss packaging solutions & assembly processes developed for next generation silicon photonics systems ranging from 100G to 800G, with a scalable path toward 1.6T & co-packaged optics. Focus will be on new device integration schemes, packaging architectures, and assembly processes geared toward high performance, high reliability networking applications. We will elaborate on these challen...Show More
Trends and Challenges in Advanced Packaging Development for Silicon Photonics Beyond 400Gbps in Hyperscale Data Center Networking Applications
Jie Xue;Sandeep Razdan;Peter De Dobbelaere;Angelo Miele;Aparna Prasad;Tong Wang;Vipul Patel;Ginni Chadha
2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Year: 2022 | Conference Paper |
Cited by: Papers (3)
Silicon photonics has emerged as a key technology for scaling high speed optical interconnects through miniaturization and increase in performance while reducing power per Gbps. In this paper, we will discuss critical silicon photonics technology building blocks and present a technology roadmap that enable transceivers 400Gbps and beyond. Challenges toward device integration, reliability and indus...Show More
3D SiP with Organic Interposer for ASIC and Memory Integration
Li Li;Pierre Chia;Paul Ton;Mohan Nagar;Sada Patil;Jie Xue;Javier Delacruz;Marius Voicu;Jack Hellings;Bill Isaacson;Mark Coor;Ross Havens
2016 IEEE 66th Electronic Components and Technology Conference (ECTC)
Year: 2016 | Conference Paper |
To meet the requirements of the next high generation high-performance networking switches and routers, system integration based on the Three-dimensional (3D) System-in-Package (SiP) technology is being studied and developed. In this paper, we report the development of a 3D SiP using the organic interposer technology. A 3D SiP is designed and manufactured with a large size organic interposer with f...Show More
Cost and performance effective silicon interposer and Vertical Interconnect for 3D ASIC and memory integration
2014 IEEE 64th Electronic Components and Technology Conference (ECTC)
Year: 2014 | Conference Paper |
Cited by: Papers (3)
To enable three-dimensional (3D) ASIC and memory integration, large-size silicon interposer is a critical technology [1]. Currently most silicon interposers are manufactured by wafer foundries and are limited in size by the wafer lithographic processing. In this study, manufacturing of cost- and performance-effective, large-size silicon interposers are investigated. The existing supply chain and i...Show More
Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications
Heng-Chieh Chien;John H. Lau;Yu-Lin Chao;Ming-Ji Dai;Ra-Min Tain;L. Li;P. Su;J. Xue;M. Brillhart
2012 IEEE 62nd Electronic Components and Technology Conference
Year: 2012 | Conference Paper |
Cited by: Papers (35)
In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the...Show More
Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration
Li Li;Peng Su;Jie Xue;Mark Brillhart;John Lau;P. J. Tzeng;C. K. Lee;C. J. Zhan;M. J. Dai;H. C. Chien;S. T. Wu
2012 IEEE 62nd Electronic Components and Technology Conference
Year: 2012 | Conference Paper |
The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed...Show More
Shear microprobing of chip-package interaction in advanced interconnect structures
A. W. Hsing;A. V. Kearney;L. Li;J. Xue;M. Brillhart;R. H. Dauskardt
2011 IEEE International Interconnect Technology Conference
Year: 2011 | Conference Paper |
Cited by: Papers (2)
Chip-package interaction has become an increasingly important concern due to higher reflow temperatures of Pb-free solders and the heterogeneous integration of materials with vastly different properties. In particular, shear stresses are common during the packaging process. In this study, a microprobe metrology system is used to assess the mechanics of advanced interconnect structures under shear ...Show More
Microprobing the mechanics of complex interconnect structures
A. W. Hsing;A. V. Kearney;L. Li;J. Xue;M. Brillhart;R. H. Dauskardt
2010 IEEE International Interconnect Technology Conference
Year: 2010 | Conference Paper |
Packaging advanced silicon devices has become increasingly challenging because the effects of stresses exerted on interconnect structures during package assembly and operation are not well understood. In this study, a microprobe metrology system is used to assess the mechanics of these interconnect structures. This allows for a better understanding of the robustness of an interconnect design and t...Show More
The interaction between grain orientation evolution and thermal cycling as a function of position in ball grid arrays using orientation image microscopy
Tae-Kyu Lee;Bite Zhou;Lauren Blair;Kuo-Chuan Liu;Jie Xue;Thomas R. Bieler
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
Year: 2010 | Conference Paper |
Cited by: Papers (2)
Thermally cycled PBGA packages with a full array of 196 solder joints after various pre-conditions are examined to observe the microstructure evolution of Sn-Ag-Cu solder joints during aging and thermal cycling, focusing on Sn grain orientation. Each PBGA package was polished to obtain plan view cross sections of every solder joint, and characterized using both Polarized Optical microscopy and Ori...Show More
Micromechanics and damage processes in interconnect structures
A. W. Hsing;A. V. Kearney;L. Li;J. Xue;M. Brillhart;R. H. Dauskardt
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
Year: 2010 | Conference Paper |
Packaging advanced silicon devices has become increasingly challenging because the effects of stresses exerted on interconnect structures during package assembly and operation are not well understood. In this study, a microprobe metrology system is used to assess the mechanics of these interconnect structures. This allows for a better understanding of the robustness of an interconnect design and t...Show More
Assembly and reliability of advanced packaging technologies in high speed networking applications
John Savic;Percy Aria;Judy Priest;Mudasir Ahmad;Ken Hubbard;Real Pomerleau;Sue Teng;Mohan Nagar;Jie Xue
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
Year: 2010 | Conference Paper |
Cited by: Papers (7)
High end networking and computing applications continue to drive silicon technologies for higher data rates and increased bandwidth. The push for silicon performance with 45nm and 32nm devices also drives a need for packaging performance to deliver clean and efficient power to the device. This paper compares the electrical performance, assembly and reliability of various advanced packaging technol...Show More
A synchrotron micro-diffraction investigation of crystallographic texture of high-Sn alloy films and its effects on whisker growth
Pylin Sarobol;Aaron Pedigo;John Blendell;Carol Handwerker;Peng Su;Li Li;Jie Xue
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
Year: 2010 | Conference Paper |
Cited by: Papers (6)
For electroplated Sn and Sn alloy finishes, one of the reliability concerns remains the risk of whisker growth. Results from recent work have suggested that whiskers are most likely to form in regions of the films where high stress or a stress gradient exists. If strain/stress distribution information can be collected at a grain-by-grain level, correlations between such information and the propens...Show More
Effects of isothermal aging and in-situ current stress on the reliability of lead-free solder joints
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
Year: 2010 | Conference Paper |
Cited by: Papers (2)
The microstructure and mechanical behavior of Sn-Ag-Cu (SAC) soldering alloys can change significantly over time when exposed to isothermal aging and in-situ current stress. Electronics assemblies built with SAC solder joints are exposed to elevated ambient temperatures and relatively high current densities for prolonged periods of time. Therefore it is important to understand the impact of these ...Show More
Pb-free solder joint reliability of fine pitch chip-scale packages
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)
Year: 2010 | Conference Paper |
Cited by: Papers (10)
Chip-scale package (CSP) is commonly seen on high density boards as it minimizes the foot print while packed more functionality into one component. Board level reliability concern over CSPs is that finer pitch limits the solder ball size attached and the stencil thickness used in assembly which leads to much smaller joint volume and standoff while larger die-to-package ratio typically means higher...Show More
Reliability of microelectronics packaging in the era of EnergyWise and Borderless networks
2010 IEEE International Reliability Physics Symposium
Year: 2010 | Conference Paper |
Cited by: Papers (3)
In an ever-increasingly connected world, the boundaries or obstacles to accessing information are being torn down by business necessity, personal preferences and technical innovations. The Borderless Network is creating the ability for customers to work anywhere, with any device using services and applications like video, collaboration, with a secure, reliable and seamless communication experience...Show More
Comparison study of effective power delivery in advanced substrate technologies for high speed networking applications
2009 International Conference on Electronic Packaging Technology & High Density Packaging
Year: 2009 | Conference Paper |
Cited by: Papers (5)
High end networking and computing applications continue to drive silicon technologies for higher data rates and increased bandwidth. The push for silicon performance also drives a need for packaging performance to deliver clean and efficient power to the device. This paper compares the electrical performance of three new advanced packaging technologies designed to improve the DC and AC power deliv...Show More
Improving board assembly yield through PBGA warpage reduction
2009 International Conference on Electronic Packaging Technology & High Density Packaging
Year: 2009 | Conference Paper |
Cited by: Papers (9)
Since its introduction in the early 1990s, plastic ball grid array (PBGA) package had become the ldquopackage of choicerdquo due to its good electrical performance, lower cost, high assembly yield and self-alignment during board assembly process. Thermo-mechanical behavior of PBGA is highly dependent on the properties of the constituent components. The relative mechanical compliances and thermal e...Show More
Impact of system level thermal solution on the interconnect reliability of high performance and high heat dissipating CSP package
Mudasir Ahmad;KC Liu;CJ Lee;Judy Priest;Sung-Ju Pak;Susheela Narasimhan;Mohan Nagar;Jie Xue
2008 58th Electronic Components and Technology Conference
Year: 2008 | Conference Paper |
Cited by: Papers (2)
A custom SRAM was developed for high performance and high reliability network switching applications using 90nm low-k silicon technology. It is a 13.6mm × 18.4mm Flip Chip Chip Scale Package (CSP) with a 11.12mm × 16.36mm die. The package has 838 BGA balls at 0.5mm pitch. The 0.5 mm ball pitch CSP minimizes electrical package parasitics and enables higher data rate performance. However, the high a...Show More
Comprehensive Assembly and Reliability Study of 0201's for High Reliability Applications for Utilizing both a Pb-Free and Sn/Pb Assembly Process
Gnyaneshwar Ramakrishna;Bala Nandagopal;Tim Dick;Anthony Burton;Reggie Higdon;Mike Anvari;Mason Hu;Sue Teng;Jie Xue
2007 Proceedings 57th Electronic Components and Technology Conference
Year: 2007 | Conference Paper |
Cited by: Papers (1)
A comprehensive study was undertaken to evaluate various board design parameters, assembly and reliability of 0201's as it relates to high reliability products. The design parameters considered included four pad designs, two trace width terminations, three orientations, three board thicknesses and four component to component spacing on a large PWB panel. The assembly parameter evaluation included,...Show More
Environmental Effects on Dielectric Films in Plastic Encapsulated Silicon Devices
Li Li;Jie Xue;Mudasir Ahmad;Mark Brillhart;Gary Lu;Zhiquan Luo;Jay Im;Paul S. Ho
2007 Proceedings 57th Electronic Components and Technology Conference
Year: 2007 | Conference Paper |
Cited by: Papers (3)
Mechanical integrity of interlayer and intralayer dielectric films and its impact on interconnect reliability has become more important as critical dimensions in ultralarge-scale integrated circuits are continuously reduced and Cu interconnect, low-k dielectrics (Cu/low-k) are widely adopted for the new technology nodes. Mechanical integrity of the dielectric films and reliability of interconnect ...Show More
Feasibility Study of a SiP for High Performance and Reliability Product Application
2005 Conference on High Density Microsystem Design and Packaging and Component Failure Analysis
Year: 2005 | Conference Paper |
Cited by: Papers (3)
For specific applications, there can be significant performance advantages when using a SiP (system in package). With the proper silicon functional partitioning, well controlled interconnect medium, and well tuned interface design; the data bandwidth can be increased by both speed and width. The disadvantages of SiPs are increased risks in reliability, manufacturability, and difficulty with test a...Show More
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