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K. Seno - IEEE Xplore Author Profile

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High-performance and low-power microprocessors are key to PDA applications. A dynamic voltage and frequency management (DVFM) scheme with leakage power compensation effect is introduced in a microprocessor with 128-bit wideband 64-Mb embedded DRAM. The DVFM scheme autonomously controls clock frequency from 8 to 123 MHz in steps of 0.5 MHz and also adaptively controls supply voltage from 0.9 to 1.6...Show More
A dynamic voltage and frequency management scheme that autonomously controls the clock frequency (8 to 123 MHz at 0.5 MHz step) and adaptively controls the voltage (0.9 to 1.6 V at 5 mV step) with a leakage power compensation effect is developed for a low-power embedded microprocessor. It achieves 82% power reduction in personal information manager (PIM) application.Show More
In multimedia applications, various video encoding/decoding standards such as MPEG2, MPEG1 and emerging algorithms call for a DSP solution of the extremely computation-intensive tasks. Several DSPs have been developed based on intensive pipeline processing at the macro-block level. In these DSPs, macroblock-based pipeline memory slices are needed for each pipeline stage. Programmability is limited...Show More
A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and pi...Show More
We developed a soft macro cell generator which generates discrete cosine transform (DCT) macro cells for various video compression requirements. Because of the proposed fast algorithm, hardware implementation, and customized flip flop cells, a generated macro cell is as small as any other full custom DCT LSI and macro cell, although the generator's output is a soft macro cell. Furthermore an equiv...Show More
A 4-Mb*4 SRAM (static random access memory) with a 9-ns access time that uses a 0.35- mu m CMOS process with KrF excimer laser lithography is descibed. The 9-ns access time is achieved by using a current-mode nonequalized read data path with an offset-reduced stabilized-feedback current sense amplifier and a quadrant-organization architecture. The design includes a current-mode wired-OR 64-b*4 par...Show More
A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35- mu m CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented.<>Show More
A multibit test (MBT) trigger circuit for megabit SRAM packages with no unused pins is discussed. The features of the MBT trigger circuit are a logic trigger mode without using any additional pins and practical use of counter circuits. The essence of trigger mode selection is that two pulses are for MBT set and three pulses are for MBT reset. In this way, a logic trigger mode that does not use NC ...Show More