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Hidetoshi Onodera - IEEE Xplore Author Profile
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Hidetoshi Onodera

Also published under: H. Onodera

Publications
219
Citations
1,581
Publications by Year
19802022
Co-Authors:
Show All Co-Authors (191)
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Hidetoshi Onodera

Also published under: H. Onodera

Affiliation

Kyoto University, Kyoto, Japan

Publication Topics

Biography

Hidetoshi Onodera (M’87–SM’12–F’18) received the B.E., M.E., and Dr. Eng. degrees in electronic engineering from Kyoto University, Kyoto, Japan.,In 1983, he joined the Department of Electronics, Kyoto University, where he is currently a Professor at the Department of Communications and Computer Engineering, Graduate School of Informatics. His current research interests include design technologies for digital, analog, and RF LSIs, with a particular emphasis on low-power design, design for manufacturability, and design for dependability.,Dr. Onodera served as a Program Chair and a General Chair of ICCAD and ASP-DAC. He was the Chairman of the Information Processing Society of Japan SIG-System LSI Design Methodology (IPSJ SIG-SLDM), the Instit...
Publications
219
Citations
1,581
Publications by Year
19802022
Co-Authors:
Show All Co-Authors (191)
Author's Published Works

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Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits

Jun Shiomi;Shogo Terada;Tohru Ishihara;Hidetoshi Onodera

2022 IEEE 35th International System-on-Chip Conference (SOCC)
Year: 2022 | Conference Paper |
This paper proposes a standard-cell memory structure with fine-grained power gating techniques for low voltage circuits. Focusing on the fact that a number of zeros appear in many applications such as artificial intelligence, power gating techniques are applied to bit cells storing zeroes only. After describing a standard-cell structure which is suitable for fine-grained power gating, this paper p...Show More

Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits

Jun Shiomi;Shogo Terada;Tohru Ishihara;Hidetoshi Onodera

Year: 2022 | Conference Paper |

Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization

Misaki Udo;Mahfuzul Islam;Hidetoshi Onodera

2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS)
Year: 2022 | Conference Paper |
Ring oscillator circuits are useful for the characterization of MOS transistors under switching operation. Accurate characterization of per-gate variation becomes difficult when the ring oscillator consists of many stages or contains heterogeneity. We propose a homogeneous ring oscillator structure with a staggered layout for the accurate characterization of per-gate characteristics. Using a heade...Show More

Homogeneous Ring Oscillator with Staggered Layout for Gate-level Delay Characterization

Misaki Udo;Mahfuzul Islam;Hidetoshi Onodera

Year: 2022 | Conference Paper |

Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region

Shoya Sonoda;Jun Shiomi;Hidetoshi Onodera

2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)
Year: 2022 | Conference Paper |
Cited by: Papers (1)
This paper refers to an optimal pair of the supply and the threshold voltages, which minimizes the energy consumption under the given delay constraint, as a minimum energy point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking algorithm over a wide operating performance region. The key point is that the accuracy required for determining the MEP is not hig...Show More

Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region

Shoya Sonoda;Jun Shiomi;Hidetoshi Onodera

Year: 2022 | Conference Paper |

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map

Yih-Lang Li;Shih-Ting Lin;Shinichi Nishizawa;Hong-Yan Su;Ming-Jie Fong;Oscar Chen;Hidetoshi Onodera

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year: 2022 | Volume: 41, Issue: 12 | Journal Article |
Cited by: Papers (1)
For the 7-nm technology node, cell placement with a drain-to-drain abutment (DDA) requires additional filler cells, increasing the placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with the optimized number of drains on cell boundary based on ASAP 7-nm PDK. We propose a DDA-aware dynamic programming-based transistor placement. Previous works ignore t...Show More

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map

Yih-Lang Li;Shih-Ting Lin;Shinichi Nishizawa;Hong-Yan Su;Ming-Jie Fong;Oscar Chen;Hidetoshi Onodera

Year: 2022 | Volume: 41, Issue: 12 | Journal Article |

Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics

Jun Shiomi;Shuya Kotsugi;Boyu Dong;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

2021 58th ACM/IEEE Design Automation Conference (DAC)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
A tamper-resistant logical operation method based on integrated nanophotonics is proposed focusing on electromagnetic side-channel attacks. In the proposed method, only the phase of each optical signal is modulated depending on its logical state, which keeps the power of optical signals in optical logic circuits constant. This provides logic-gate-level tamper resistance which is difficult to achie...Show More

Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics

Jun Shiomi;Shuya Kotsugi;Boyu Dong;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

Year: 2021 | Conference Paper |

CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models

Kensuke Murakami;Mahfuzul Islam;Hidetoshi Onodera

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)
Year: 2021 | Conference Paper |
Cited by: Papers (3)
This paper proposes a parameter extraction method by comparing the cumulative distribution functions (CDF) between measurement and model-based estimation. We propose a nonlinear delay variation model for fast Monte Carlo simulation to obtain CDFs. We demonstrate the validity of our method by extracting within-die and random telegraph noise induced threshold voltage variations using measured data o...Show More

CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models

Kensuke Murakami;Mahfuzul Islam;Hidetoshi Onodera

Year: 2021 | Conference Paper |

MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching

Hongjie Xu;Jun Shiomi;Hidetoshi Onodera

IEEE Open Journal of Circuits and Systems
Year: 2021 | Volume: 2 | Journal Article |
Cited by: Papers (1)
The irregular data access pattern caused by sparsity brings great challenges to efficient processing accelerators. Focusing on the index-matching property in DNN, this article aims to decompose sparse DNN processing into easy-to-handle processing tasks to maintain the utilization of processing elements. According to the proposed sparse processing dataflow, this article proposes an efficient genera...Show More

MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching

Hongjie Xu;Jun Shiomi;Hidetoshi Onodera

Year: 2021 | Volume: 2 | Journal Article |

Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region

Shoya Sonoda;Jun Shiomi;Hidetoshi Onodera

2020 IEEE 33rd International System-on-Chip Conference (SOCC)
Year: 2020 | Conference Paper |
Cited by: Papers (2)
This paper proposes a runtime voltage-scaling method that optimizes the supply voltage (Vdd) and the threshold voltage (Vth) under a given delay constraint. This paper refers to the optimal voltage pair as a Minimum Energy Point (MEP). This paper firstly proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold regi...Show More

Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region

Shoya Sonoda;Jun Shiomi;Hidetoshi Onodera

Year: 2020 | Conference Paper |

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics

Jun Shiomi;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

2020 International Conference on Rebooting Computing (ICRC)
Year: 2020 | Conference Paper |
The emergence of nanophotonic devices has enabled to design light-speed on-chip optical circuits with extremely low latency. This paper proposes an optical implementation of scalable Deep Neural Networks (DNNs) enabling light-speed inference. The key issue in optical neural networks is the scalability limited by area, power and the number of available wavelengths. Due to the scalability, it is thu...Show More

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics

Jun Shiomi;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

Year: 2020 | Conference Paper |

A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias

Kentaro Nagai;Jun Shiomi;Hidetoshi Onodera

2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Year: 2020 | Conference Paper |
Cited by: Papers (3)
This paper proposes an area- and energy-efficient DLL-based body bias generator (BBG) for minimum energy operation that controls p-well and n-well bias independently so that the BBG can minimize total energy consumption under a skewed process condition between nMOSFETs and pMOSFETs. The proposed BBG is composed of digital cells compatible with cell-based design, which results in low energy consump...Show More

A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias

Kentaro Nagai;Jun Shiomi;Hidetoshi Onodera

Year: 2020 | Conference Paper |

MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing

Yih-Lang Li;Shih-Ting Lin;Shinichi Nishizawa;Hidetoshi Onodera

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)
Year: 2020 | Conference Paper |
Multi-row cell structure has become popular for modern designs, especially for the multi-bit flip-flop (MBFF) cells, but has not been under full investigation in previous cell library synthesis researches. In this work, we propose an entire placement and routing flow for synthesizing multi-row cell layouts. The proposed new A*-based multi-row transistor placement algorithm can optimize the intra-r...Show More

MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing

Yih-Lang Li;Shih-Ting Lin;Shinichi Nishizawa;Hidetoshi Onodera

Year: 2020 | Conference Paper |

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing

Ryosuke Matsuo;Jun Shiomi;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Year: 2020 | Conference Paper |
Cited by: Papers (3)
Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high...Show More

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing

Ryosuke Matsuo;Jun Shiomi;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

Year: 2020 | Conference Paper |

Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning

Misaki Udo;Kensuke Murakami;A.K.M. Mahfuzul Islam;Hidetoshi Onodera

2020 IEEE 33rd International Conference on Microelectronic Test Structures (ICMTS)
Year: 2020 | Conference Paper |
Dynamic back-gate voltage tuning is an effective technique for run-time optimization of energy consumption in an LSI. In this paper, we present our observation that variability due to RTN under back-gate voltage tuning increases significantly at low voltage operation. We investigate on the mechanism of the increase of variability and its impact on circuit performance using a ring oscillator based ...Show More

Increased Delay Variability due to Random Telegraph Noise under Dynamic Back-gate Tuning

Misaki Udo;Kensuke Murakami;A.K.M. Mahfuzul Islam;Hidetoshi Onodera

Year: 2020 | Conference Paper |

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

Masanori Hashimoto;Xu Bai;Naoki Banno;Munehiro Tada;Toshitsugu Sakamoto;Jaehoon Yu;Ryutaro Doi;Yusuke Araki;Hidetoshi Onodera;Takashi Imagawa;Hirovuki Ochi;Kazutoshi Wakabayashi;Yukio Mitsuyama;Tadahiko Suuibayashi

2020 IEEE International Solid-State Circuits Conference - (ISSCC)
Year: 2020 | Conference Paper |
Cited by: Papers (7)
FPGAs are a suitable platform for implementing up-to-date machine learning algorithms and state-of-the-art AI applications including inference engines in embedded systems and training accelerators in cloud systems. Despite its short design turn-around time, the achievable performance is limited by the low area efficiency originating from field programmability [1]–[2]. Also, data transfer minimizat...Show More

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

Masanori Hashimoto;Xu Bai;Naoki Banno;Munehiro Tada;Toshitsugu Sakamoto;Jaehoon Yu;Ryutaro Doi;Yusuke Araki;Hidetoshi Onodera;Takashi Imagawa;Hirovuki Ochi;Kazutoshi Wakabayashi;Yukio Mitsuyama;Tadahiko Suuibayashi

Year: 2020 | Conference Paper |

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS

Akira Tsuchiya;Akitaka Hiratsuka;Kenji Tanaka;Hiroyuki Fukuyama;Naoki Miura;Hideyuki Nosaka;Hidetoshi Onodera

2019 32nd IEEE International System-on-Chip Conference (SOCC)
Year: 2019 | Conference Paper |
Cited by: Papers (6)
This paper demonstrates a small area, high speed and low power CMOS transimpedance amplifier (TIA) for optical communication. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Based on the bandwidth and energy per bit estimation, we designed a 5-stage INV-TIA and on-chip inductors ...Show More

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS

Akira Tsuchiya;Akitaka Hiratsuka;Kenji Tanaka;Hiroyuki Fukuyama;Naoki Miura;Hideyuki Nosaka;Hidetoshi Onodera

Year: 2019 | Conference Paper |

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map

Yih-Lang Li;Shih-Ting Lin;Shinichi Nishizawa;Hong-Yan Su;Ming-Jie Fong;Oscar Chen;Hidetoshi Onodera

2019 56th ACM/IEEE Design Automation Conference (DAC)
Year: 2019 | Conference Paper |
Cited by: Papers (7)
For 7nm technology node, cell placement with drain-to-drain abutment (DDA) requires additional filler cells, increasing placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with optimized number of drains on cell boundary based on ASAP 7nm PDK. We propose a DDA-aware dynamic programming based transistor placement. Previous works ignore the use of M0 lay...Show More

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map

Yih-Lang Li;Shih-Ting Lin;Shinichi Nishizawa;Hong-Yan Su;Ming-Jie Fong;Oscar Chen;Hidetoshi Onodera

Year: 2019 | Conference Paper |

Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA

Naoki Banno;Koichiro Okamoto;Noriyuki Iguchi;Hiroyuki Ochi;Hidetoshi Onodera;Masanori Hashimoto;Tadahiko Sugibayashi;Toshitsugu Sakamoto;Munehiro Tada

IEEE Transactions on Electron Devices
Year: 2019 | Volume: 66, Issue: 8 | Journal Article |
Cited by: Papers (8)
A nonvolatile and programmable routing switch featuring two-varistor selected complementary atom switch (2V-1CAS also known as via-switch) is evaluated. The a-Si/SiN/a-Si varistor as a selector for the atom switch shows superior nonlinear current–voltage characteristics with high selectivity of ~105, which originates from the staircase barrier height in the layers. The two control lines connected ...Show More

Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA

Naoki Banno;Koichiro Okamoto;Noriyuki Iguchi;Hiroyuki Ochi;Hidetoshi Onodera;Masanori Hashimoto;Tadahiko Sugibayashi;Toshitsugu Sakamoto;Munehiro Tada

Year: 2019 | Volume: 66, Issue: 8 | Journal Article |

Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation

A.K.M. Mahfuzul Islam;Ryota Shimizu;Hidetoshi Onodera

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)
Year: 2019 | Conference Paper |
Cited by: Papers (2)
We present measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On- Thin-Buried-Oxide process. Measurement results reveal that the expected value of delay fluctuation decreases rapidly with the increase of logic depth. However, the delay fluctuation above 99th percentile is not...Show More

Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation

A.K.M. Mahfuzul Islam;Ryota Shimizu;Hidetoshi Onodera

Year: 2019 | Conference Paper |

Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators

A.K.M. Mahfuzul Islam;Ryota Shimizu;Hidetoshi Onodera

2019 IEEE International Reliability Physics Symposium (IRPS)
Year: 2019 | Conference Paper |
We present measurement results of delay fluctuations induced by random telegraph noise (RTN) from 154k 7-stage ring oscillators (RO). Measurement results are obtained from test chips fabricated in a 65-nm Silicon-On-Thin-Buried-Oxide process. Measurement results reveal that RTN-induced frequency fluctuation which corresponds to the underlying threshold voltage deviation follows lognormal distribut...Show More

Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators

A.K.M. Mahfuzul Islam;Ryota Shimizu;Hidetoshi Onodera

Year: 2019 | Conference Paper |

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics

Takumi Egawa;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Shota Kita;Kengo Nozaki;Kenta Takata;Masaya Notomi

2018 IEEE International Conference on Rebooting Computing (ICRC)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
Optical circuits constructed using nanophotonic logic gates have attracted significant attention due to its ultra low-latency operation. This paper first introduces conventional optical logic circuits and their issues when the number of inputs is large. Then, we propose a method of minimizing the latency of large fan-in optical logic circuits using a multi-level optimization method. The proposed o...Show More

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics

Takumi Egawa;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Shota Kita;Kengo Nozaki;Kenta Takata;Masaya Notomi

Year: 2018 | Conference Paper |

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing

Jun Shiomi;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

2018 IEEE International Conference on Rebooting Computing (ICRC)
Year: 2018 | Conference Paper |
Cited by: Papers (2)
The emergence of nanophotonic devices has enabled to design integrated optical circuits for ultra-high speed on-chip signal processing. This paper proposes an optical implementation of an approximate parallel multiplier for two n-bit integers. The key to ultra-high speed processing is to reduce the number of OptoElectric (OE) converters on a critical path since the OE converters dominantly determi...Show More

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing

Jun Shiomi;Tohru Ishihara;Hidetoshi Onodera;Akihiko Shinya;Masaya Notomi

Year: 2018 | Conference Paper |

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology

Toshiyuki Inoue;Ryosuke Noguchi;Akira Tsuchiya;Keiji Kishine;Hidetoshi Onodera

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Year: 2018 | Conference Paper |
We report a low-power and high-linearity inductorless low-noise amplifier (LNA) with active-shunt-feedback in 65nm CMOS technology. Noise-cancelling was shown to be achieved by adding a coupling capacitor between NMOS and PMOS amplifiers and adjusting its capacitance in a circuit simulation. The measured frequency response of the power gain had good agreement with the post-layout simulated results...Show More

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology

Toshiyuki Inoue;Ryosuke Noguchi;Akira Tsuchiya;Keiji Kishine;Hidetoshi Onodera

Year: 2018 | Conference Paper |

Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization

Tatsuhiro Higuchi;Tohru Ishihara;Hidetoshi Onodera

2018 31st IEEE International System-on-Chip Conference (SOCC)
Year: 2018 | Conference Paper |
This paper discusses performance modeling for FPGA (Field Programmable Gate Array) which uses an emerging switching device called a via-switch for programmable interconnects and logic configurations. With the derived model, we can evaluate how the overall chip-level performance is affected by various design parameters such as device characteristics, threshold voltages, layout structures, FPGA arch...Show More

Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization

Tatsuhiro Higuchi;Tohru Ishihara;Hidetoshi Onodera

Year: 2018 | Conference Paper |

PVT2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process

A.K.M. Mahfuzul Islam;Hidetoshi Onodera

2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Year: 2018 | Conference Paper |
Cited by: Papers (5)
In addition to the conventional PVT (Process, Voltage and Temperature) variation, time-dependent current fluctuation such as random telegraph noise (RTN) poses a new challenge on VLSI reliability. In this paper, we show that compared with the static random variation, RTN amplitude of a particular device is not constant across supply voltages and temperatures. A device may show large RTN amplitude ...Show More

PVT2: Process, Voltage, Temperature and Time-dependent Variability in Scaled CMOS Process

A.K.M. Mahfuzul Islam;Hidetoshi Onodera

Year: 2018 | Conference Paper |

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation

Akitaka Hiratsuka;Akira Tsuchiya;Kenji Tanaka;Hiroyuki Fukuyama;Naoki Miura;Hideyuki Nosaka;Hidetoshi Onodera

2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Year: 2018 | Conference Paper |
Cited by: Papers (5)
This paper presents a low-noise and high-speed transimpedance amplifier (TIA) for optical interconnection. For high density parallel integration of optical receiver, small area and crosstalk mitigation arc important as well as high speed, low power and so on. We propose an inverter TIA (INV-TIA) with inductor-less bandwidth compensation circuits and a passive crosstalk filter. Since these addition...Show More

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation

Akitaka Hiratsuka;Akira Tsuchiya;Kenji Tanaka;Hiroyuki Fukuyama;Naoki Miura;Hideyuki Nosaka;Hidetoshi Onodera

Year: 2018 | Conference Paper |

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