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Quek Li Chuang - IEEE Xplore Author Profile

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Author details

Quek Li Chuang

Publications

2

Citations

0

Publications by Year

20232024

Co-Authors:

Lee Chia ChengAng Boon ChongNordin Nor FarahanimAbd Aziz Nurul HazirahPhang Eng Hong

Show All Co-Authors (8)

Quek Li Chuang

Affiliation

Intel, Malaysia

Publication Topics

Electronic Design Automation,
Technology Node,
Cell Coverage,
Circuit Design,
Combinational Logic,
Design Space,
Design Space Exploration,
External Nodes,
General Design,
Integrated Circuit Design,
Internal Efficiency,
Internet Of Things

Publications

2

Citations

0

Publications by Year

20232024

Co-Authors:

Lee Chia Cheng
Ang Boon Chong
Nordin Nor Farahanim
Abd Aziz Nurul Hazirah
Phang Eng Hong

Show All Co-Authors (8)

Author's Published Works

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Showing 1-2 of 2 results

Conferences (2)

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Single Year
Quek Li Chuang(2)
Lee Chia Cheng(2)
Nordin Nor Farahanim(2)
Phang Eng Hong(2)
Koh Jid Ian(2)
Intel, Malaysia(2)
2023 6th International Conference on Electronics Technology (ICET)(1)
2024 IEEE Symposium on Industrial Electronics & Applications (ISIEA)(1)
IEEE(2)
Chengdu, China(1)
Kuala Lumpur, Malaysia(1)
Electronic Design Automation(2)
Technology Node(2)
Cell Coverage(1)
Circuit Design(1)
Combinational Logic(1)

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Design Space Exploration with Machine Learning Co-Optimization

Quek Li Chuang;Ang Boon Chong;Lee Chia Cheng;Koh Jid Ian;Nordin Nor Farahanim;Mei Ghee Lok;Phang Eng Hong

2024 IEEE Symposium on Industrial Electronics & Applications (ISIEA)

Year: 2024 | Conference Paper |

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In recent years, electronic design automation has been preoccupied with machine learning. The application of machine learning is being utilized by the design industry to increase the predictability of physical design and signoff. Presently, machine learning applications in the field of integrated circuit design are primarily concerned with yield modeling, lithography hotspot identification, noise ...Show More

Design Space Exploration with Machine Learning Co-Optimization

Quek Li Chuang;Ang Boon Chong;Lee Chia Cheng;Koh Jid Ian;Nordin Nor Farahanim;Mei Ghee Lok;Phang Eng Hong

2024 IEEE Symposium on Industrial Electronics & Applications (ISIEA)

Year: 2024 | Conference Paper |

Pre-silicon ASIC Library Validation

Ang Boon Chong;Quek Li Chuang;Lee Chia Cheng;Koh Jid Ian;Tan Say Hong;Phang Eng Hong;Abd Aziz Nurul Hazirah;Nordin Nor Farahanim

2023 6th International Conference on Electronics Technology (ICET)

Year: 2023 | Conference Paper |

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For standard cell design, it will go through ASIC regression with multiple design block. It can be high performance block design convergence, digital signal processing block, processor core design block as well as a few synthesis block. In most cases, the intention is to verify the standard cell collateral release is in good quality. However, the standard cell instantiation depends on the function...Show More

Pre-silicon ASIC Library Validation

Ang Boon Chong;Quek Li Chuang;Lee Chia Cheng;Koh Jid Ian;Tan Say Hong;Phang Eng Hong;Abd Aziz Nurul Hazirah;Nordin Nor Farahanim

2023 6th International Conference on Electronics Technology (ICET)

Year: 2023 | Conference Paper |

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Contact & Support

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