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Dummy filling methods for reducing interconnect capacitance and number of fills

A. Kurokawa;T. Kanamoto;T. Ibe;A. Kasebe;Chang Wei Fong;T. Kage;Y. Inoue;H. Masuda

Sixth international symposium on quality electronic design (isqed'05)

Year: 2005 | Conference Paper |

Cited by: Papers (23) | Patents (100)

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In recent system-on-chip (SoC) designs, floating dummy metals inserted for planarization have created serious problems because of increased interconnect capacitance and the enormous amount of fill required. We present new methods to reduce the interconnect capacitance and the amount of dummy metals needed. These techniques include three ways of filling: (1) improved floating square fills, (2) floa...Show More

Dummy filling methods for reducing interconnect capacitance and number of fills

A. Kurokawa;T. Kanamoto;T. Ibe;A. Kasebe;Chang Wei Fong;T. Kage;Y. Inoue;H. Masuda

Sixth international symposium on quality electronic design (isqed'05)

Year: 2005 | Conference Paper |

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