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K. Natori - IEEE Xplore Author Profile

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Ni silicide film, formed by stacked structure of nickel and silicon, have been fabricated by RF magnetron sputtering using different gas species. The resistivity of the silicide films have been measured. While the resistivity of the film with Ar gas sputtering gradually decreases with higher annealing temperature, films with Kr gas sputtering show resistivity as low as the bulk ones in a wide proc...Show More
In this paper we use the p+-Si and n+-Si as bottom electrode for CeO2 based ReRAM. The work function difference between p+-Si and n+-Si substrate gives out an about 0.6 V shift of the set and reset voltage. The mechanism of this shift was investigated and the set and reset of voltage with pulse width dependence was also concerned depends on p+-Si substrate.Show More
Thermal oxidation of SiC(0001) substrates with La2O3 capped annealing has been performed. La2O3 capped oxidation has shown improvements in reduced hysteresis and interface state density (Dit) for MOS capacitors. La-silicate grains, agglomerated at the step bunches of SiC substrates, have been confirmed upon oxidation. We can anticipated that La-silicate grains are likely to passivate the charge tr...Show More
In this paper, Enhanced oxidation of SiC(0001) substrates using La2O3 capped annealing has been presented. Compared to thermal oxidation, lower oxidation temperature can be implemented to form SiO2 layer, owing to higher oxidation rate by 10 times with La2O3 capped oxidation by catalytic effect of the film. Although oxidation kinetics are based on oxidation through step faces, the roughness of cre...Show More
In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect transistors (FETs) operating in sub-22-nm CMOS technologies. Employing a coupled drift-diffusion room temperature carrier transport formulation, with 2-D quantum confinement effects, we numerically simulate Si GAA NWF...Show More
Contributions of gate metal to electrical characteristics in AlGaN/GaN Schottky HEMT are reported. The focus is on the collapse of drain current associated with Schottky metals. Ni and W gate introduce electrically active defects under the gate metal in AlGaN layer. These electrically active defects induce the current collapse, higher gate leakage current, and frequency dispersion in $C{-}V$ char...Show More
Metal induced effects on electrical characteristics in AlGaN/GaN Schottky HEMT are reported. Focus is given to the collapse of drain current attributed to Schottky metal. Of particular interest for discussion is that TiN gate can suppresses the collapse of drain current compared with conventional Ni gate. Nitrogen concentrations in TiN gate are found to be correlated to the current collapse, indic...Show More
Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT< 0.5 nm), Dit as low as 8.0×1011 (cm−2 eV−1) and thermal stability up to 600°C is demonstrated by using La2O3 as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.Show More
We have attempted to make a current density equation for n-diamond. By taking both band and nearest-neighbor hopping conductions into account, the resistivity of reported experimental data can be reconstructed. By introducing average mobility, which is a weighted average of each mobility, current density equation for n-diamond can be expressed.Show More
Ni silicide with the nanowire line width down to 15 nm was formed by the reaction of Ni thin films with Si nanowires. The electrical analyses revealed that Ni2Si was formed on all Si nanowires having width in the range from 15 to 80 nm. However, a drastic increase in the resistivity was observed for the width smaller than 35 nm. The reason for this increase is discussed in terms of roughness in li...Show More
La-silicate/Si interface were investigated by measuring C-V characteristics and infra-red absorbance spectra. Interface state density (Dit) down to 1010 cm−2/eV was obtained by annealing at temperature over 800 °C. A red-shift due to Si-O-Si LO phonon toward 1250 cm−1 was found. We speculate that relaxation of SiO4 networks in Lasilicates results in low Dit.Show More
This paper reports on detailed comparison between (100)- and (110)-oriented nMOSFETs with direct contact of La-silicate/Si interface structure for expansion to multi-gate architecture including FinFETs, trigate FETs, and nanowire FETs. Scaled EOT of 0.73 nm for (110)-oriented nMOSFETs has been achieved as well as (100)-oriented nMOSFETs. Although the large interface state density originating from ...Show More
We investigated the diameter-dependent performance of Si and InAs nanowire metal–oxide–semiconductor field-effect transistors (NW MOSFETs) by developing a gate capacitance model. A nonparabolic effective-mass approximation and a semiclassical ballistic transport model were used. The capacitance model helped interpret the different contributions of the capacitances, which were due to the inversion-...Show More
This letter focuses on studying the characteristic behavior of oxygen in La-silicate dielectrics by comparison with $\hbox{HfO}_{2}$ dielectrics. ${V}_{\rm FB}$ shift of La-silicate caused by oxygen annealing is found to be stable even after reduction annealing unlike with $\hbox{HfO}_{2}$. Moreover, reduced gate leakage current and improved effective mobility of nMOSFETs with La-silicate are obs...Show More
This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to $\hbox{1.6} \times \hbox{10}^{11}\ \hbox{cm}^{-2}\hbox{eV}^{-1}$ by annealing at 800 $^{\circ}\hbox{C}$ for...Show More
A compact model for the quasi-ballistic silicon nanowire MOSFET was developed by supplementing the ballistic framework previously disclosed by us with an original carrier-scattering model. The scattering model considers elastic scattering and optical phonon emission, which is the dominant route of energy relaxation in the device. The quasi-ballistic electric current showed a remarkable decrease co...Show More
This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm−2 eV−1 can be achieved by annealing at 800 °C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibi...Show More
The effect of isotropic and anisotropic scattering within the drain region of diode with ballistic channel is investigated using the semiclassical Monte Carlo simulation, and the results are discussed. The results show that the isotropic scattering can severely degrade the steady-state current, the electrons mean velocity, and increase the electrons concentration in channel because some hot electr...Show More
Compact modeling of a Si nanowire MOSFET is discussed. Framework and detailed expression of the compact model for a ballistic Si nanowire MOSFET are provided. The device characteristics of a thin Si nanowire MOSFET is shown as a model calculation, and some characteristic features of the device are explained. Then a new scattering model for a quasi- ballistic Si nanowire MOSFET is introduced, and t...Show More
Gate semi-around silicon nanowire (SiNW) FETs have been fabricated and their electrical characteristics, especially on the drivability, have been assessed for future high performance devices. Among different wire size, a SiNW FET with a cross-section of 12×19 nm2 has shown an improvement in the on-current (ION) when normalized by the channel peripheral length. A high ION over 1600 µA/µm at an over...Show More
A demonstration of VFB/Vth tuning has been conducted by optimized annealing in oxygen ambient for direct contact of high-k with Si gate stacks. The amount of oxygen atoms has been controlled by optimized annealing temperature and the thickness of the gate electrode. The shift in VFB has been confirmed irrespective of gate dielectric materials and the thickness. The Vth of pMOSFET can be controlled...Show More
Because of its nature of effectively suppressing the off-leakage current with gate around configuration, the Si nanowire FET has been thought be the ultimate structure for for ultra-small CMOS devices towards their downsizing limit. Recently, several experimental data of Si nanowire FETs with very high on-current much larger than that of planar MOSFETs have been published. Thus, Si nanowire FETs a...Show More
A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (Vfb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicat...Show More