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Yao Xin - IEEE Xplore Author Profile
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Yao Xin

Publications
9
Citations
25
Publications by Year
20212025
Co-Authors:
Show All Co-Authors (27)
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Yao Xin

Affiliation

Cyberspace Institute of Advanced Technology
Guangzhou University
Guangzhou, China
Huangpu Research School of Guangzhou University, Guangzhou, China

Publication Topics

Biography

Yao Xin received the Ph.D. degree from the Department of Electronic Engineering, City University of Hong Kong, Hong Kong, in 2015. He was a Visiting Research Scholar with the University of Southern California, USA, in 2014. Currently, he is an Associate Professor with the Cyberspace Institute of Advanced Technology, Guangzhou University, Guangdong, China. His research interests include network intelligent hardware acceleration, VLSI design for deep learning, and network algorithms.(Based on document published on 10 October 2024).
Publications
9
Citations
25
Publications by Year
20212025
Co-Authors:
Show All Co-Authors (27)
Author's Published Works

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A Heterogeneous and Adaptive Architecture for Decision-Tree-Based ACL Engine on FPGA

Yao Xin;Chengjun Jia;Wenjun Li;Ori Rottenstreich;Yang Xu;Gaogang Xie;Zhihong Tian;Jun Li

IEEE Transactions on Computers
Year: 2025 | Volume: 74, Issue: 1 | Journal Article |
Access Control Lists (ACLs) are crucial for ensuring the security and integrity of modern cloud and carrier networks by regulating access to sensitive information and resources. However, previous software and hardware implementations no longer meet the requirements of modern datacenters. The emergence of FPGA-based SmartNICs presents an opportunity to offload ACL functions from the host CPU, leadi...Show More

A Heterogeneous and Adaptive Architecture for Decision-Tree-Based ACL Engine on FPGA

Yao Xin;Chengjun Jia;Wenjun Li;Ori Rottenstreich;Yang Xu;Gaogang Xie;Zhihong Tian;Jun Li

Year: 2025 | Volume: 74, Issue: 1 | Journal Article |

Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA

Yao Xin;Wenjun Li;Chengjun Jia;Xianfeng Li;Yang Xu;Bin Liu;Zhihong Tian;Weizhe Zhang

IEEE/ACM Transactions on Networking
Year: 2024 | Volume: 32, Issue: 2 | Journal Article |
Cited by: Papers (1)
As a programmable accelerator, SmartNIC provides more opportunities for algorithmic packet classification. Our aim in this work is to achieve both line-speed rule search and efficient rule update, two highly desired metrics for SDN data plane. We leverage the parallelism offered by the FPGA in SmartNIC following an algorithm/hardware co-design paradigm. Particularly, we first design an algorithm t...Show More

Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA

Yao Xin;Wenjun Li;Chengjun Jia;Xianfeng Li;Yang Xu;Bin Liu;Zhihong Tian;Weizhe Zhang

Year: 2024 | Volume: 32, Issue: 2 | Journal Article |

A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

Yao Xin;Wenjun Li;Gaogang Xie;Yang Xu;Yi Wang

IEEE Micro
Year: 2023 | Volume: 43, Issue: 2 | Magazine Article |
Cited by: Papers (6)
As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast rule search and efficient rule update for large-scale rule sets. In this article, we design and implement a novel architecture for mult...Show More

A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

Yao Xin;Wenjun Li;Gaogang Xie;Yang Xu;Yi Wang

Year: 2023 | Volume: 43, Issue: 2 | Magazine Article |

Updatable Packet Classification on FPGA with Bounded Worst-Case Performance

Yao Xin;Wenjun Li;Gaogang Xie;Yang Xu;Yi Wang

2022 IEEE Symposium on High-Performance Interconnects (HOTI)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
FPGA has been recognized as an attractive acceler-ator for line-speed packet classification in SmartNIC due to its ability to reconfigure and provide massive parallelism. As a promising algorithmic approach that can fully exploit the FPGA characteristics, decision tree based packet classification on FPGA has been actively investigated in the past decade. However, most of them suffer from unbalance...Show More

Updatable Packet Classification on FPGA with Bounded Worst-Case Performance

Yao Xin;Wenjun Li;Gaogang Xie;Yang Xu;Yi Wang

Year: 2022 | Conference Paper |

FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree

Yao Xin;Wenjun Li;Guoming Tang;Tong Yang;Xiaohe Hu;Yi Wang

IEEE/ACM Transactions on Networking
Year: 2022 | Volume: 30, Issue: 6 | Journal Article |
Cited by: Papers (8)
OpenFlow switches are being deployed in SDN to enable a wide spectrum of non-traditional applications. As a promising alternative to brutal force TCAMs, FPGA-based packet classification is being actively investigated. However, none of the existing FPGA designs can achieve high performance on both search and update for large-scale rule sets. To address this issue, we propose TcbTree, an FPGA-based ...Show More

FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree

Yao Xin;Wenjun Li;Guoming Tang;Tong Yang;Xiaohe Hu;Yi Wang

Year: 2022 | Volume: 30, Issue: 6 | Journal Article |

AdderIC: Towards Low Computation Cost Image Compression

Bowen Li;Yao Xin;Chao Li;Youneng Bao;Fanyang Meng;Yongsheng Liang

ICASSP 2022 - 2022 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
Recently, learned image compression methods have shown their outstanding rate-distortion performance when compared to traditional frameworks. Although numerous progress has been made in learned image compression, the computation cost is still at a high level. To address this problem, we propose AdderIC, which utilizes adder neural networks (AdderNet) to construct an image compression framework. Ac...Show More

AdderIC: Towards Low Computation Cost Image Compression

Bowen Li;Yao Xin;Chao Li;Youneng Bao;Fanyang Meng;Yongsheng Liang

Year: 2022 | Conference Paper |

High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection

Yao Xin;Donglong Chen;Chongyang Zeng;Weichen Zhang;Yi Wang;Ray C. C. Cheung

IEEE Transactions on Computers
Year: 2022 | Volume: 71, Issue: 7 | Journal Article |
Cited by: Papers (3)
Rotation Region Proposal Networks (RRPN) are used to generate rotated proposals with the information of text angle for arbitrary oriented scene text detection (STD). However, the computational complexity of RRPN inference is relatively high compared with other methods, which makes it difficult for massive deployment. In this paper, the first full-stack FPGA-CPU heterogeneous system design of RRPN-...Show More

High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection

Yao Xin;Donglong Chen;Chongyang Zeng;Weichen Zhang;Yi Wang;Ray C. C. Cheung

Year: 2022 | Volume: 71, Issue: 7 | Journal Article |

An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets

Yao Xin;Wenjun Li;Yi Wang;Song Yao

IEEE INFOCOM 2021 - IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS)
Year: 2021 | Conference Paper |
Cited by: Papers (3)
A high-performance packet classification architecture based on FPGA supporting large-scale rule sets up to 100k is proposed in this poster. It supports fast dynamic rule update and tree reconstruction. The update throughput is comparable to that of classification. An efficient data structure set for decision tree is constructed to convert tree traversal to addressing process. Different levels of p...Show More

An FPGA-based High-Throughput Packet Classification Architecture Supporting Dynamic Updates for Large-Scale Rule Sets

Yao Xin;Wenjun Li;Yi Wang;Song Yao

Year: 2021 | Conference Paper |

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