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Denis Tremblay - IEEE Xplore Author Profile

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A pixel configuration based on a gate-controlled lateral thyristor (GC-LT) is proposed to achieve low-light-level extension with a high dynamic range (HDR). Our previous work has demonstrated that the GC-LT has a high sensitivity in low-light-level conditions, and the trigger time is sensitive to the optical power ranging from 1\times 10^{-{9}} to 2.5\times 10^{-{6}} W/cm2. In this article...Show More
Thyristors operated at switching point are highly sensitive to external physical signals such as light or temperature. However, due to the instability of sensitive switching point, conventional thyristors are commonly used as optical switches and hardly applied for low-light level detection. In this work, a silicon-based gate-controlled lateral thyristor (GC-LT), which takes advantage of high sens...Show More
Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive...Show More
Non-volatile memory (NVM) based computing-in-memory (CIM) shows significant advantages in handling deep learning tasks for artificial intelligence (AI) applications. To overcome the decreasing cost effectiveness of transistor scaling and the intrinsic inefficiency of data-shuttling in the von-Neumann architecture, CIM is proposed to realize high-speed and low-power system with parallel multiplicat...Show More
A novel True Random Number Generator (TRNG) based on analog RRAM is developed. For the first time, the proposed TRNG harvests the variation of the pulse number in programming the analog states as the random source, and utilizes the parity of the pulse number to generate random bits. The TRNG throughput reaches >1 Mbit/sec for a single cell. The feasibility for chip-level parallel operation on mult...Show More
Neural network accelerators are widely deployed in application systems for computer vision, speech recognition, and machine translation. Due to ubiquitous deployment of these systems, a strong incentive rises for adversaries to attack such artificial intelligence (AI) systems. Trojan is one of the most important attack models in hardware security domain. Hardware Trojans are malicious modification...Show More
Physically unclonable functions (PUFs) are promising primitives for hardware security with wide applications in the lnternet of Things (IoT), e.g., authentication and encryption key generation [1, 2]. Most silicon PUFs utilize process variability of semiconductor manufacturing [1, 3, 4]. These implementations are sensitive to variations in operating conditions (e.g., supply voltage and temperature...Show More
This paper reports the design, fabrication, and test of a 3-D integrated uncooled focal plane array (FPA) using monocrystalline silicon diodes as thermosensitive devices. The diode array is fabricated from the silicon device layer of a silicon-on-insulator wafer, and the readout integrated circuits (ROICs) are fabricated on a bulk wafer using the CMOS technology. The silicon diode array is vertica...Show More
With the globalization of semiconductor industry, hardware security issues have been gaining increasing attention. Among all hardware security threats, the insertion of hardware Trojans is one of the main concerns. Meanwhile, many current Trojan detection solutions follow the assumption that the hardware Trojan itself should be composed of digital logic. This assumption is invalidated by recently ...Show More
In the present study, a TaOx/HfO2-based resistive random access memory (RRAM) device was developed to generate self-selective feature. After appropriate current compliance in the set process, a threshold switching phenomenon was observed in the reset process. Satisfactory results were gained for the cycle-to-cycle and device-to-device uniform in the following measurements, which was of great signi...Show More
With the globalization of semiconductor industry, hardware security issues have been gaining increasing attention. Among all hardware security threats, the insertion of hardware Trojans is one of the main concerns. Meanwhile, many current Trojan detection solutions follow the assumption that the hardware Trojan itself should be composed of digital logic. This assumption is invalidated by recently ...Show More
RRAM is a promising electrical synaptic device for efficient neuromorphic computing. A human face recognition task was demonstrated on a 1k-bit 1T1R array using an online training perceptron network. The RRAM device structure and materials stack were optimized to achieve reliable bidirectional analog switching behavior. A binarized-hidden-layer (BHL) circuit architecture is proposed to minimize th...Show More
Physical unclonable function (PUF) is an important hardware security primitive. This paper proposes a novel PUF design based on a double-layer RRAM array architecture and digital RRAM programming achieved by splitting resistance distribution after a continuous distribution was formed. The proposed PUF was implemented on a 16 Mb RRAM test chip and its randomness was verified with NIST test suite. T...Show More
The retention requirements of analog RRAM for neuromorphic computing applications are quite different from conventional RRAM for memory applications. Meanwhile, filamentary analog RRAM exhibits different retention behavior in comparison to strong-filament RRAM. For the first time, the statistical behaviors of read current noise and retention in a 1Kb filamentary analog RRAM array are investigated ...Show More
FinFET variability, which is a small amplitude deviation caused by process, cannot be ignored with the scaling of CMOS. This work utilizes the variability as the random source of SRAM Physical Unclonable function (PUF). The impact of the variation has been simulated from device-level to circuit-level. Further research has been done with its influence on SRAM static noise margin (SNM) and SRAM PUF ...Show More
This paper systematically analyzed the tradeoff between writing operation time and tail bit of LRS, and provided the optimal writing operation time for 1T1R RRAM with the target LRS 500kn and HRS 10Mn. Under three different cases of pulse width, the experiment results all show that the optimal voltage amplitude and step could achieve a good tradeoff between writing operation time and tail bits of ...Show More
This paper systematically analyzed and optimized the operation parameters of low current 1T1R RRAM arrays. Considering both thermal and electrical field driven effects, a current and voltage joint verification strategy has been proposed. Highly uniform multilevel resistive switching performances with LRS resistance higher than 100kΩ and HRS resistance higher than 10MΩ were obtained on 130nm CMOS p...Show More
A 16Mb RRAM Chip with source line (SL) current limitation and a novel programming strategy is developed. Comparing with traditional gate control current method, SET operation with source current control can significantly narrow the read current distribution. The programming strategy is optimized simultaneously using a low current multi-step forming and single pulse program operation. With these op...Show More
RRAM-based physical unclonable function (PUF) leveraging the remarkable resistance variability has been proposed and experimentally demonstrated on a 1-kb one-transistor one-resistor array. In this letter, a novel differential read-out method is utilized to reduce the effect of resistance window degradation. The RRAM PUF reliability is optimized through a reliability-enhancement design and oxide s...Show More
A technical challenge in fabrication of ultra-thin sensor chip (UTSC) is to keep chip integrity in debonding the ultra-thin chips from grinding facilities. This paper presents a new debonding method by utilizing a thermally decomposable polypropylene carbonate (PPC), as the temporary bonding adhesive. Because PPC can readily decompose at relatively low temperature, this method can maintain the chi...Show More
As more and more demand on high density storage, 3D NAND Flash memories have developed into multi-level cell and triple-level cell. With the charge-trapping technology adopted in 3D NAND Flash, it is possible to achieve quadruple-level-cell (QLC) which brings higher density capability. Meanwhile, the program coding method makes significant impact on the efficiency of the lockout operation in the p...Show More
A readout circuit for flash memory threshold voltage distribution is proposed in this paper. This circuit includes ramp generator circuit, comparator and 9-bit counter which converts threshold voltage into digital outputs. Besides, word line and bit line decoder, high voltage generator, bias module and timing control circuit are integrated as peripheral circuit. This chip is fabricated by 0.13 μm ...Show More
In this work, optimized signal transmission schemes are proposed to improve the signal transmission speed and area efficiency of high density embedded DRAM (eDRAM). As in the schemes, overdrive scheme is adopted to enhance the drive capability of read word-line (RWL) inverters and reduce inverters area overhead, optimized signal transmission path scheme is proposed to reduce signal transmission lo...Show More
The unique tail bits retention failure behavior is observed in the RRAM array. Unlike the previous reports on single device or the average value''s retention behavior, quick retention loss of tail bits is found for both LRS and HRS. By statistically characterized such relaxation effect of tail bits, physical models are built to quantitatively describe the relaxation behaviors of LRS and HRS. The c...Show More
Three-dimensional integration of microelectromechanical systems (MEMS) and CMOS is able to achieve hetero-integrated microsystems with high performance, small size, low cost, and multiple functions. This paper reports a 3-D integration method using wafer transfer technology and electroless Ni plating with a noncontact induction (ENPNI) technique. Wafer transfer technology based on adhesive bonding...Show More