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Jia Zheng

Publications

Citations

354

Publications by Year

20192022

Co-Authors:

Ning BiXili DaiShenghua GaoKun HuangLei Jin

Show All Co-Authors (27)

Jia Zheng

Affiliation

Manycore Tech Inc.

Publication Topics

Convolutional Neural Network,
Room Layout,
Boundary Map,
Bounding Box,
Depth Estimation,
Depth Map,
Line Of Work,
Parameter Plane,
2D Plane,
2D Projection,
3D Geometry,
3D Plane

Biography

Jia Zheng received the B.E. degree from Northwestern Polytechnical University, Xi’an, China, in 2016. He is currently pursuing the Ph.D. degree with ShanghaiTech University, Shanghai, China.(Based on document published on 12 September 2019).

Publications

Citations

354

Publications by Year

20192022

Co-Authors:

Ning Bi
Xili Dai
Shenghua Gao
Kun Huang
Lei Jin

Show All Co-Authors (27)

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Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology

S. Qiao;S. Moran;D. Srinivas;S. Pamarti;S. S. Iyer

2022 International Electron Devices Meeting (IEDM)

Year: 2022 | Conference Paper |

Cited by: Papers (2)

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Most analog compute-in-memory (CIM) devices suffer from low on/off ratio, large IR drop, limited retention capability, the need for an additional access device, and additional process complexity for embedding in commercial CMOS logic. To overcome these disadvantages, the charge-trap transistor (CTT) has been proposed. It uses commercial off-the-shelf technology (22 FDX demonstrated in this work) w...Show More

Demonstration of Analog Compute-In-Memory Using the Charge-Trap Transistor in 22 FDX Technology

S. Qiao;S. Moran;D. Srinivas;S. Pamarti;S. S. Iyer

2022 International Electron Devices Meeting (IEDM)

Year: 2022 | Conference Paper |

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