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Tianliang Zhang - IEEE Xplore Author Profile

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Author details

Tianliang Zhang

Also published under: T. Zhang

Publications

17

Citations

19

Publications by Year

20182024

Co-Authors:

Mustafa Al-QadiSamadian AzadehBalagangadhar G. BathulaChristophe BetouleMartin Birk

Show All Co-Authors (40)

Tianliang Zhang

Also published under: T. Zhang

Affiliation

Department of Electrical and Computer Engineering, The University of Texas at Dallas, Texas

Publication Topics

Optical Networks,
Transportation Network,
Wavelength Division Multiplexing,
Bit Error Rate,
Optical Transport,
Data Rate,
Network Elements,
Optical Amplifier,
Performance Monitoring,
Physical Layer,
Polynomial Regression,
Service Quality

Biography

Tianliang Zhang was born in Nanjing, China in 1994. He received the B.S. degree in optoelectronic information engineering from the Nanjing University of Science and Technology, Nanjing, China, in 2016. He is currently working toward the M.S. and Ph.D. degrees in electrical engineering with the University of Texas at Dallas, Richardson, TX, USA. His research interests are optical networks modeling and optical communication system impairment analysis.(Based on document published on 21 June 2019).

Publications

17

Citations

19

Publications by Year

20182024

Co-Authors:

Mustafa Al-Qadi
Samadian Azadeh
Balagangadhar G. Bathula
Christophe Betoule
Martin Birk

Show All Co-Authors (40)

Author's Published Works

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Showing 1-22 of 22 results

Conferences (13)

Journals (9)

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Weihua Zhang(22)
Haibo Chen(11)
Binyu Zang(6)
Haojun Wang(5)
Pen-Chung Yew(5)
Parallel Processing Institute, Fudan University, Shanghai, China(10)
Institute of Parallel and Distributed Systems, Shanghai Jiaotong University, Shanghai, China(7)
Software School, Fudan University, Shanghai, China(5)
Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, USA(2)
Parallel Processing Institute, Fudan University(2)
IEEE Transactions on Parallel and Distributed Systems(7)
(IEEE ISPASS) IEEE International Symposium on Performance Analysis of Systems and Software(1)
16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)(1)
2012 41st International Conference on Parallel Processing(1)
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)(1)
IEEE(22)
San Francisco, CA, USA(2)
Athens, Greece(1)
Austin, TX, USA(1)
Beijing, China(1)
Brasov, Romania(1)
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Parallelization(6)
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A System-Level Dynamic Binary Translator Using Automatically-Learned Translation Rules

Jinhu Jiang;Chaoyi Liang;Rongchao Dong;Zhaohui Yang;Zhongjun Zhou;Wenwen Wang;Pen-Chung Yew;Weihua Zhang

2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

Year: 2024 | Conference Paper |

Cited by: Papers (1)

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System-level emulators have been used extensively for the design, debugging and evaluation of the system software. They work by providing a system-level virtual machine that can support a guest operating system (OS) running on a platform with the same or different native OS using the same or different instruction-set architecture. For such a system-level emulation, dynamic binary translation (DBT)...Show More

A System-Level Dynamic Binary Translator Using Automatically-Learned Translation Rules

Jinhu Jiang;Chaoyi Liang;Rongchao Dong;Zhaohui Yang;Zhongjun Zhou;Wenwen Wang;Pen-Chung Yew;Weihua Zhang

2024 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

Year: 2024 | Conference Paper |

More with Less – Deriving More Translation Rules with Less Training Data for DBTs Using Parameterization

Jinhu Jiang;Rongchao Dong;Zhongjun Zhou;Changheng Song;Wenwen Wang;Pen-Chung Yew;Weihua Zhang

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Year: 2020 | Conference Paper |

Cited by: Papers (7)

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Dynamic binary translation (DBT) is widely used in system virtualization and many other important applications. To achieve a higher translation quality, a learning-based approach has been recently proposed to automatically learn semantically-equivalent translation rules. Because translation rules directly impact the quality and performance of the translated host codes, one of the key issues is to ...Show More

More with Less – Deriving More Translation Rules with Less Training Data for DBTs Using Parameterization

Jinhu Jiang;Rongchao Dong;Zhongjun Zhou;Changheng Song;Wenwen Wang;Pen-Chung Yew;Weihua Zhang

2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

Year: 2020 | Conference Paper |

Architectural Support for NVRAM Persistence in GPUs

Sui Chen;Lei Liu;Weihua Zhang;Lu Peng

IEEE Transactions on Parallel and Distributed Systems

Year: 2020 | Volume: 31, Issue: 5 | Journal Article |

Cited by: Papers (3)

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Non-volatile Random Access Memories (NVRAM) have emerged in recent years to bridge the performance gap between the main memory and external storage devices, such as Solid State Drives (SSD). In addition to higher storage density, NVRAM provides byte-addressability, higher bandwidth, near-DRAM latency, and easier access compared to block devices such as traditional SSDs. This enables new programmin...Show More

Architectural Support for NVRAM Persistence in GPUs

Sui Chen;Lei Liu;Weihua Zhang;Lu Peng

IEEE Transactions on Parallel and Distributed Systems

Year: 2020 | Volume: 31, Issue: 5 | Journal Article |

A High Throughput B+tree for SIMD Architectures

Weihua Zhang;Zhaofeng Yan;Yuzhe Lin;Chuanlei Zhao;Lu Peng

IEEE Transactions on Parallel and Distributed Systems

Year: 2020 | Volume: 31, Issue: 3 | Journal Article |

Cited by: Papers (10)

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B+tree is one of the most important data structures and has been widely used in different fields. With the increase of concurrent queries and data-scale in storage, designing an efficient B+tree structure has become critical. Due to abundant computation resources, SIMD architectures provide potential opportunities to achieve high query throughput for B+tree. However, prior methods cannot achieve s...Show More

A High Throughput B+tree for SIMD Architectures

Weihua Zhang;Zhaofeng Yan;Yuzhe Lin;Chuanlei Zhao;Lu Peng

IEEE Transactions on Parallel and Distributed Systems

Year: 2020 | Volume: 31, Issue: 3 | Journal Article |

Eunomia: Scaling Concurrent Index Structures Under Contention Using HTM

Weihua Zhang;Xin Wang;Shiyu Ji;Ziyun Wei;Zhaoguo Wang;Haibo Chen

IEEE Transactions on Parallel and Distributed Systems

Year: 2018 | Volume: 29, Issue: 8 | Journal Article |

Cited by: Papers (3)

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Hardware transactional memory (HTM) is an emerging hardware feature. HTM simplifies the programming model of concurrent programs while preserving high and scalable performance. With the commercial availability of HTM-capable processors, HTM has recently been adopted to construct efficient concurrent index structures. However, with the expansion of data volume and user amount, data management syste...Show More

Eunomia: Scaling Concurrent Index Structures Under Contention Using HTM

Weihua Zhang;Xin Wang;Shiyu Ji;Ziyun Wei;Zhaoguo Wang;Haibo Chen

IEEE Transactions on Parallel and Distributed Systems

Year: 2018 | Volume: 29, Issue: 8 | Journal Article |

qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses

Shaoming Chen;Lu Peng;Samuel Irving;Zhou Zhao;Weihua Zhang;Ashok Srivastava

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2018 | Volume: 37, Issue: 1 | Journal Article |

Cited by: Papers (1)

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Multisocket computer systems are popular in workstations and servers. However, they suffer from the relatively low bandwidth of intersocket communication especially for massive parallel workloads that generate many intersocket requests for synchronizations and remote memory accesses. Intersocket traffic puts pressure on the underlying network connecting all processors with a limited bandwidth conf...Show More

qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses

Shaoming Chen;Lu Peng;Samuel Irving;Zhou Zhao;Weihua Zhang;Ashok Srivastava

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Year: 2018 | Volume: 37, Issue: 1 | Journal Article |

Prophet: A Parallel Instruction-Oriented Many-Core Simulator

Weihua Zhang;Xiaofeng Ji;Yunping Lu;Haojun Wang;Haibo Chen;Pen-Chung Yew

IEEE Transactions on Parallel and Distributed Systems

Year: 2017 | Volume: 28, Issue: 10 | Journal Article |

Cited by: Papers (6)

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Most existing computer architecture simulators are cycle oriented, i.e., they are driven cycle by cycle. However, frequent switches among simulation contexts, excessive buffer accesses and tightly coupled manner often make such an architecture simulator slow, difficult to parallelize and hard to scale to large-scale many-core systems. In this paper, we propose Prophet, a parallel instruction-orien...Show More

Prophet: A Parallel Instruction-Oriented Many-Core Simulator

Weihua Zhang;Xiaofeng Ji;Yunping Lu;Haojun Wang;Haibo Chen;Pen-Chung Yew

IEEE Transactions on Parallel and Distributed Systems

Year: 2017 | Volume: 28, Issue: 10 | Journal Article |

VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multi-Core

Weihua Zhang;Xiaofeng Ji;Bo Song;Shiqiang Yu;Haibo Chen;Tao Li;Pen-Chung Yew;Wenyun Zhao

IEEE Transactions on Parallel and Distributed Systems

Year: 2017 | Volume: 28, Issue: 4 | Journal Article |

Cited by: Papers (10)

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The non-deterministic nature of multi-threaded workloads running on multi-core platforms often leads to notable performance variability from run to run. Such variability makes experimental results prone to misinterpretations or misguided claims. To deal with such variability, statistical inference methods are usually used to summarize the experimental results with certain confidence levels by runn...Show More

VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multi-Core

Weihua Zhang;Xiaofeng Ji;Bo Song;Shiqiang Yu;Haibo Chen;Tao Li;Pen-Chung Yew;Wenyun Zhao

IEEE Transactions on Parallel and Distributed Systems

Year: 2017 | Volume: 28, Issue: 4 | Journal Article |

FPGA-Based Parallel Implementation of SURF Algorithm

Wenjie Chen;Shuaishuai Ding;Zhilei Chai;Daojing He;Weihua Zhang;Guanhua Zhang;Qiwei Peng;Wang Luo

2016 IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS)

Year: 2016 | Conference Paper |

Cited by: Papers (16)

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SURF (Speeded up robust features) detection is used extensively in object detection, tracking and matching. However, due to its high complexity, it is usually a challenge to perform such detection in real time on a general-purpose processor. This paper proposes a parallel computing algorithm for the fast computation of SURF, which is specially designed for FPGAs. By efficiently exploiting the adva...Show More

FPGA-Based Parallel Implementation of SURF Algorithm

Wenjie Chen;Shuaishuai Ding;Zhilei Chai;Daojing He;Weihua Zhang;Guanhua Zhang;Qiwei Peng;Wang Luo

2016 IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS)

Year: 2016 | Conference Paper |

Understanding the Architectural Characteristics of EDA Algorithms

Xin Wang;Xiaofeng Ji;Yunping Lu;Yi Li;Weijia Zhou;Weihua Zhang;Wenyun Zhao

2016 45th International Conference on Parallel Processing (ICPP)

Year: 2016 | Conference Paper |

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Currently, the release of different chip products has come to a burst. Time-to-market period of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects try to shorten every design and manufacture stage. Therefore, it has become one of the major concerns for them that how to accelerate electronic design automation (EDA) tools, which h...Show More

Understanding the Architectural Characteristics of EDA Algorithms

Xin Wang;Xiaofeng Ji;Yunping Lu;Yi Li;Weijia Zhou;Weihua Zhang;Wenyun Zhao

2016 45th International Conference on Parallel Processing (ICPP)

Year: 2016 | Conference Paper |

Performance Analysis of Multimedia Retrieval Workloads Running on Multicores

Yunping Lu;Xin Wang;Weihua Zhang;Haibo Chen;Lu Peng;Wenyun Zhao

IEEE Transactions on Parallel and Distributed Systems

Year: 2016 | Volume: 27, Issue: 11 | Journal Article |

Cited by: Papers (6)

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Multimedia data has become a major data type in the Big Data era. The explosive volume of such data and the increasing real-time requirement to retrieve useful information from it have put significant pressure in processing such data in a timely fashion. However, while prior efforts have done in-depth analysis on architectural characteristics of traditional multimedia processing and text-based ret...Show More

Performance Analysis of Multimedia Retrieval Workloads Running on Multicores

Yunping Lu;Xin Wang;Weihua Zhang;Haibo Chen;Lu Peng;Wenyun Zhao

IEEE Transactions on Parallel and Distributed Systems

Year: 2016 | Volume: 27, Issue: 11 | Journal Article |

Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures

Weihua Zhang;Shiqiang Yu;Haojun Wang;Zhuofang Dai;Haibo Chen

IEEE Transactions on Computers

Year: 2016 | Volume: 65, Issue: 10 | Journal Article |

Cited by: Papers (2)

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Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most h...Show More

Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures

Weihua Zhang;Shiqiang Yu;Haojun Wang;Zhuofang Dai;Haibo Chen

IEEE Transactions on Computers

Year: 2016 | Volume: 65, Issue: 10 | Journal Article |

A Loosely-Coupled Full-System Multicore Simulation Framework

Weihua Zhang;Haojun Wang;Yunping Lu;Haibo Chen;Wenyun Zhao

IEEE Transactions on Parallel and Distributed Systems

Year: 2016 | Volume: 27, Issue: 6 | Journal Article |

Cited by: Papers (3)

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Full-system simulation is critical in evaluating design alternatives for multicore processors. However, state-of-the-art multicore simulators either lack good extensibility due to their tightly-coupled design between functional model (FM) and timing model (TM), or cannot guarantee cycle-accuracy. This paper conducts a comprehensive study on factors affecting cycle-accuracy and uncovers several con...Show More

A Loosely-Coupled Full-System Multicore Simulation Framework

Weihua Zhang;Haojun Wang;Yunping Lu;Haibo Chen;Wenyun Zhao

IEEE Transactions on Parallel and Distributed Systems

Year: 2016 | Volume: 27, Issue: 6 | Journal Article |

Characterizing Multi-media Retrieval Applications

Yunping Lu;Xin Wang;Weihua Zhang;Yi Li;Wenyun Zhao

2015 44th International Conference on Parallel Processing

Year: 2015 | Conference Paper |

Cited by: Papers (1)

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Multimedia data, especially image and video data, have become one of the most overwhelming data types on the Internet recently. Considering the user experience and real application requirements, multimedia data always demand a real-time processing speed. As a result, the huge amount of such data make retrieving useful information from them not only data-intensive, but also computation-intensive, w...Show More

Characterizing Multi-media Retrieval Applications

Yunping Lu;Xin Wang;Weihua Zhang;Yi Li;Wenyun Zhao

2015 44th International Conference on Parallel Processing

Year: 2015 | Conference Paper |

Hydra: Efficient Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architecture

Zhuofang Dai;Haojun Wang;Weihua Zhang;Haibo Chen;Binyu Zang

2014 43rd International Conference on Parallel Processing

Year: 2014 | Conference Paper |

HTML

Detecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most h...Show More

Hydra: Efficient Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architecture

Zhuofang Dai;Haojun Wang;Weihua Zhang;Haibo Chen;Binyu Zang

2014 43rd International Conference on Parallel Processing

Year: 2014 | Conference Paper |

RPSim: A Rapid Prototyping Full-System Simulator for SoC Software Development

Haojun Wang;Qinghao Min;Yi Li;Weihua Zhang

2014 9th IEEE International Conference on Networking, Architecture, and Storage

Year: 2014 | Conference Paper |

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Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platfo...Show More

RPSim: A Rapid Prototyping Full-System Simulator for SoC Software Development

Haojun Wang;Qinghao Min;Yi Li;Weihua Zhang

2014 9th IEEE International Conference on Networking, Architecture, and Storage

Year: 2014 | Conference Paper |

DAPs: Dynamic adjustment and partial sampling for multithreaded/multicore simulation

Chien-Chih Chen;Yin-Chi Peng;Cheng-Fen Chen;Wei-Shan Wu;Qinghao Min;Pen-Chung Yew;Weihua Zhang;Tien-Fu Chen

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

Year: 2014 | Conference Paper |

Cited by: Papers (5)

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Faced with increasingly large multicore chip designs, architects need fast and accurate simulations for their exploration of design spaces within a limited simulation time budget. In multithreaded applications, threads cannot run simultaneously. Sampling is commonly used to reduce simulation time, but conventional sampling barely detects the instantaneous program variations of synchronization even...Show More

DAPs: Dynamic adjustment and partial sampling for multithreaded/multicore simulation

Chien-Chih Chen;Yin-Chi Peng;Cheng-Fen Chen;Wei-Shan Wu;Qinghao Min;Pen-Chung Yew;Weihua Zhang;Tien-Fu Chen

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

Year: 2014 | Conference Paper |

Multi-level phase analysis for sampling simulation

Jiaxin Li;Weihua Zhang;Haibo Chen;Binyu Zang

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2013 | Conference Paper |

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Extremely long simulation time of architectural simulators has been a major impediment to their wide applicability. To accelerate architectural simulation, prior researchers have proposed representative sampling simulation to trade small loss of accuracy for notable speed improvement. Generally, they use fine-grained phase analysis to select only a small representative portion of program execution...Show More

Multi-level phase analysis for sampling simulation

Jiaxin Li;Weihua Zhang;Haibo Chen;Binyu Zang

2013 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Year: 2013 | Conference Paper |

Adaptive Pipeline Parallelism for Image Feature Extraction Algorithms

Peng Chen;Donglei Yang;Weihua Zhang;Yi Li;Binyu Zang;Haibo Chen

2012 41st International Conference on Parallel Processing

Year: 2012 | Conference Paper |

Cited by: Papers (4) | Patents (1)

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Currently, multimedia data has become one of the major data types processed and transferred on the Internet. With the rapid growth of multimedia data, it is vitally important to find an efficient way to extract useful information from a large amount of data. SIFT and SURF, as the most popular multimedia feature extraction algorithms, have been widely used in many applications. However, the limited...Show More

Adaptive Pipeline Parallelism for Image Feature Extraction Algorithms

Peng Chen;Donglei Yang;Weihua Zhang;Yi Li;Binyu Zang;Haibo Chen

2012 41st International Conference on Parallel Processing

Year: 2012 | Conference Paper |

Transformer: A functional-driven cycle-accurate multicore simulator

Zhenman Fang;Qinghao Min;Keyong Zhou;Yi Lu;Yibin Hu;Weihua Zhang;Haibo Chen;Jian Li;Binyu Zang

DAC Design Automation Conference 2012

Year: 2012 | Conference Paper |

Cited by: Papers (1)

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Full-system simulators are extremely useful in evaluating design alternatives for multicore. However, state-of-the-art multicore simulators either lack good extensibility due to their tightly-coupled design between functional model (FM) and timing model (TM), or cannot guarantee cycle-accuracy. This paper conducts a comprehensive study on factors affecting cycle-accuracy and uncovers several contr...Show More

Transformer: A functional-driven cycle-accurate multicore simulator

Zhenman Fang;Qinghao Min;Keyong Zhou;Yi Lu;Yibin Hu;Weihua Zhang;Haibo Chen;Jian Li;Binyu Zang

DAC Design Automation Conference 2012

Year: 2012 | Conference Paper |

A comprehensive analysis and parallelization of an image retrieval algorithm

Zhenman Fang;Donglei Yang;Weihua Zhang;Haibo Chen;Binyu Zang

(IEEE ISPASS) IEEE International Symposium on Performance Analysis of Systems and Software

Year: 2011 | Conference Paper |

Cited by: Papers (9)

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The prevalence of the Internet and cloud computing has made multimedia data, such as image data and video data, become major data types in our daily life. For example, many data-intensive applications, such as health care and video recommendation, involve collecting, indexing and retrieving tera-scale multimedia data every day. With such a huge amount of multimedia data to process, the processing ...Show More

A comprehensive analysis and parallelization of an image retrieval algorithm

Zhenman Fang;Donglei Yang;Weihua Zhang;Haibo Chen;Binyu Zang

(IEEE ISPASS) IEEE International Symposium on Performance Analysis of Systems and Software

Year: 2011 | Conference Paper |

Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors

Weihua Zhang;Tao Bao;Binyu Zang;Chuanqi Zhu

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

Year: 2007 | Conference Paper |

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In recent years, multimedia and game applications have experienced rapid growth at an explosive rate both in quantity and complexity. Since these applications typically demand 1010 to 1011 operations to be executed per second, higher processing capability is expected. Therefore, stream processors are becoming popular because of its performance advantages in the domains of signal processing, multim...Show More

Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors

Weihua Zhang;Tao Bao;Binyu Zang;Chuanqi Zhu

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

Year: 2007 | Conference Paper |

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